Abstract: An apparatus and method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having a symmetrical interconnect system for attaching one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped poles can be arranged on the same side of a chip in an opposing fashion, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads.

Abstract: A method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having asymmetrical interconnect system for one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped holes can be arranged on the same side of the ship in an opposing action, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chips surfaces, such that antenna substrates can be attached to both the top and bottom of the chip to form a product “sandwich”, whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.

Abstract: A polymer stencil is applied to the active surface of a wafer. The stencil has openings that at least partially overlay associated metallization pads on the wafer and divider strips positioned between adjacent openings. The divider strips are arranged to overlay portions of associated metallization pads so that at least two adjacent openings overlay portions of each metallization pad. After the stencil has been positioned, a solder paste is applied to the stencil openings. The solder paste may then be reflowed with the polymer stencil remaining in place. The solder naturally creeps under the stencil so that unitary solder bumps are formed on each metallization pad. The described methods and arrangements can be used to create low profile solder bumps that are not attainable using conventional solder bump formation techniques.

Abstract: An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each contact pad. A metal layer fills the vias and forms a metallization pad that is suitable for supporting a solder bump. Preferably the metal layer extends over at least portions of the passivation layer to form a unified under bump metallization pad over the associated contact pad. Each metallization pad is electrically connected to the contact pad through a plurality of the vias. The described under bump structures can be formed at the wafer level.

Abstract: A polymer stencil is applied to the active surface of a wafer. The stencil has openings that at least partially overlay associated metallization pads on the wafer and divider strips positioned between adjacent openings. The divider strips are arranged to overlay portions of associated metallization pads so that at least two adjacent openings overlay portions of each metallization pad. After the stencil has been positioned, a solder paste is applied to the stencil openings. The solder paste may then be reflowed with the polymer stencil remaining in place. The solder naturally creeps under the stencil so that unitary solder bumps are formed on each metallization pad. The described methods and arrangements can be used to create low profile solder bumps that are not attainable using conventional solder bump formation techniques.

Abstract: An apparatus and method for attaching antennae to RFID tags is disclosed. Included is the use of RFID tags having a symmetrical interconnect system for attaching one or more antennae, such that virtually any rotational orientation of the RFID tag will result in a successful antennae attachment. Two oversized and “L” shaped gold-bumped poles can be arranged on the same side of a chip in an opposing fashion, such that at least one axis of symmetry is formed. Accordingly, virtually all rotational orientations of the chip are then acceptable when attaching a pair of opposing pole antenna leads. Alternatively, a pair of poles can be located on opposing chip surfaces, such that antenna substrates can attach to both the top and bottom of the chip to form a product “sandwich,” whereby the rotational orientation of the chip is irrelevant at an antenna attachment step.

Abstract: An apparatus and method for providing aluminum free under bump metallization stacks in an integrated circuit device is disclosed. Included is the use of vias having substantially non-vertical sidewalls that are formed in a resilient layer, such as benzocyclobutene. In general, semiconductor wafers having a plurality of dice are created, with each die having a plurality of contact pads that are formed on the active surface of the wafer. One or more passivation layers are formed on the active surface and etched appropriately to form vias coupled to the contact pads. At least one resilient layer is then disposed atop the top passivation layer and etched appropriately to form vias aligned with and smaller than the passivation layer vias, such that at least part of the contact pads but no part of the passivation layer is exposed. A plurality of UBM stacks are then formed atop the exposed contact pads and resilient layer, with each UBM stack having a plurality of layers, none of which are aluminum layers.

Abstract: A flip chip semiconductor package with an integral heat sink is disclosed as well as a technique for creating individual heat sinks by applying a conductive layer to the back surface of a wafer containing integrated circuitry before singulation. According to one aspect of the invention, an adhesive layer is applied to the back surface of a semiconductor wafer. A layer of conductive material such as copper is then attached to the back surface of the wafer using the previously applied adhesive. The wafer is then singulated to create individual semiconductor packages with superior heat transfer properties.

Abstract: An apparatus and method for scribing a semiconductor wafer coated with a substantially opaque material using vision recognition is disclosed. The apparatus includes a stage configured to hold a wafer, an imaging unit configured to generate an image of the wafer, and a computer configured to identify the coordinates of the scribe lines on the wafer from the image. During operation, the wafer is imaged using the imaging unit. The computer then identifies the coordinates of the scribe lines on the wafer from the image. Thereafter the coordinates are provided to a dicing machine which performs the dicing of the wafer. Accuracy is therefore improved since the dicing machine relies on the coordinates of the scribe lines as opposed to attempting to recognize the scribe lines through the opaque material. According to various embodiments of the invention, the imaging unit may use infrared, X-ray or ultrasound waves to generate the image of the wafer.

Abstract: An apparatus and method for scribing a semiconductor wafer coated with a substantially opaque material using vision recognition is disclosed. The apparatus includes a stage configured to hold a wafer, an imaging unit configured to generate an image of the wafer, and a computer configured to identify the coordinates of the scribe lines on the wafer from the image. During operation, the wafer is imaged using the imaging unit. The computer then identifies the coordinates of the scribe lines on the wafer from the image. Thereafter the coordinates are provided to a dicing machine which performs the dicing of the wafer. Accuracy is therefore improved since the dicing machine relies on the coordinates of the scribe lines as opposed to attempting to recognize the scribe lines through the opaque material. According to various embodiments of the invention, the imaging unit may use infrared, X-ray or ultrasound waves to generate the image of the wafer.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Abstract: A chip-on-chip integrated circuit package is disclosed. The device includes a substrate having a plurality of conductive landings disposed on a first surface thereof, a first die that is positioned over a substrate, and a second die that is mounted on the first die. The first die has a plurality of I/O pads that face away from the substrate. The second die includes a first set of contacts that mate with the conductive landings on the substrate and a second set of contacts that mate with the I/O pads on the first die. In a preferred embodiment, the first set of contacts on the second die take the form of a first set of solder bumps, and the second set of contacts on the second die take the form of a second set of solder bumps.