Patents by Inventor Nikhil Vishwanath Kelkar
Nikhil Vishwanath Kelkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200266159Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.Type: ApplicationFiled: March 8, 2017Publication date: August 20, 2020Inventors: ZAKI MOUSSAOUI, Nikhil Vishwanath Kelkar
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Patent number: 10643959Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.Type: GrantFiled: March 8, 2017Date of Patent: May 5, 2020Assignee: Intersil Americas LLCInventors: Zaki Moussaoui, Nikhil Vishwanath Kelkar
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Patent number: 9723766Abstract: An embodiment of a power-supply module includes a package having sides, a first power-supply component disposed in the package, and an electromagnetic-interference (EMI) shield disposed adjacent to two sides of the package. For example, such a module may include component-mounting platforms (e.g., a lead frame or printed circuit board) on the top and bottom sides of the module, and these platforms may provide a level of EMI shielding specified for a particular application. Consequently, such a module may provide better EMI shielding than modules with shielding along only one side (e.g., the bottom) of the module. Moreover, if the module components are mounted to, or otherwise thermally coupled to, the shielding platforms, then the module may provide multi-side cooling of the components.Type: GrantFiled: February 25, 2011Date of Patent: August 1, 2017Assignee: INTERSIL AMERICAS LLCInventors: Jian Yin, Nikhil Vishwanath Kelkar, Michael Althar
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Publication number: 20170179048Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2017Inventors: ZAKI MOUSSAOUI, Nikhil Vishwanath Kelkar
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Publication number: 20170162488Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Inventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, JR.
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Patent number: 9613889Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.Type: GrantFiled: March 19, 2015Date of Patent: April 4, 2017Assignee: Intersil Americas LLCInventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, Jr.
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Patent number: 9607917Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.Type: GrantFiled: December 7, 2010Date of Patent: March 28, 2017Assignee: Intersil Americas LLCInventors: Zaki Moussaoui, Nikhil Vishwanath Kelkar
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Publication number: 20150194370Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.Type: ApplicationFiled: March 19, 2015Publication date: July 9, 2015Inventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, JR.
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Patent number: 9012267Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.Type: GrantFiled: April 11, 2013Date of Patent: April 21, 2015Assignee: Intersil Americas LLCInventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, Jr.
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Patent number: 8951847Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.Type: GrantFiled: September 12, 2012Date of Patent: February 10, 2015Assignee: Intersil Americas LLCInventors: Nikhil Vishwanath Kelkar, Kai Liu
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Patent number: 8946875Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.Type: GrantFiled: September 27, 2012Date of Patent: February 3, 2015Assignee: Intersil Americas LLCInventors: Nikhil Vishwanath Kelkar, Lynn Wiese, Viraj Ajit Patwardhan
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Publication number: 20130313694Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.Type: ApplicationFiled: April 11, 2013Publication date: November 28, 2013Applicant: INTERSIL AMERICAS LLCInventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, JR.
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Publication number: 20130270701Abstract: A semiconductor package comprises a bond pad formed on a first semiconductor die, a surface of the bond pad exposed through an opening in a passivation layer on the first semiconductor die; a raised conductive area formed on top of a passivation layer on a second semiconductor die; and a bond wire having a first end coupled to the bond pad via a ball bond and a second end coupled directly to a surface of the raised conductive area via a stitch bond. The raised conductive area is comprised of a plurality of metal layers, each of the metal layers comprised of a respective material and having a respective thickness. The thickness and material of at least one of the plurality of metal layers is selected such that a hardness of the raised conductive area is at least as hard as a hardness of the bond wire.Type: ApplicationFiled: June 29, 2012Publication date: October 17, 2013Applicant: INTERSIL AMERICAS LLCInventors: Randolph Cruz, Nikhil Vishwanath Kelkar
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Patent number: 8558396Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.Type: GrantFiled: December 14, 2011Date of Patent: October 15, 2013Assignee: Intersil Americas Inc.Inventors: Nikhil Vishwanath Kelkar, Sagar Pushpala, Seshasayee sS. Ankireddi
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Publication number: 20130181332Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.Type: ApplicationFiled: September 12, 2012Publication date: July 18, 2013Applicant: INTERSIL AMERICAS LLCInventors: Nikhil Vishwanath Kelkar, Kai Liu
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Patent number: 8445998Abstract: A semiconductor package includes a lead structure upon which a semiconductor die is mounted with at least some portion of at least some of the leads extending to, at, or across an axis or axis of the package to militate against thermally induced growth of the package and the reduce or minimize strain within the package and reliability issue associated therewith.Type: GrantFiled: February 24, 2010Date of Patent: May 21, 2013Assignee: Intersil Americas Inc.Inventors: Young-Gon Kim, Nikhil Vishwanath Kelkar, Louis Elliott Pflughaupt
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Publication number: 20130015592Abstract: A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads.Type: ApplicationFiled: December 14, 2011Publication date: January 17, 2013Applicant: INTERSIL AMERICAS INC.Inventors: Nikhil Vishwanath Kelkar, Sagar Pushpala, Seshasayee sS. Ankireddi
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Publication number: 20120290255Abstract: A method for optical isolation in a clear mold package is provided. The method comprises forming a substrate and mounting a first component on the substrate. The method also comprises depositing a clear layer over the first component and the substrate and fabricating a trench in the clear layer near the first component, wherein the trench extends from a top surface of the substrate to the top surface of the clear layer. Further, the method comprises depositing an opaque material within the trench.Type: ApplicationFiled: September 20, 2011Publication date: November 15, 2012Applicant: Intersil Americas Inc.Inventors: Nikhil Vishwanath Kelkar, Viraj Ajit Patwardhan, Santhiran Nadarajah, Matt Preston
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Publication number: 20120063038Abstract: An embodiment of a power-supply module includes a package having sides, a first power-supply component disposed in the package, and an electromagnetic-interference (EMI) shield disposed adjacent to two sides of the package. For example, such a module may include component-mounting platforms (e.g., a lead frame or printed circuit board) on the top and bottom sides of the module, and these platforms may provide a level of EMI shielding specified for a particular application. Consequently, such a module may provide better EMI shielding than modules with shielding along only one side (e.g., the bottom) of the module. Moreover, if the module components are mounted to, or otherwise thermally coupled to, the shielding platforms, then the module may provide multi-side cooling of the components.Type: ApplicationFiled: February 25, 2011Publication date: March 15, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Jian YIN, Nikhil Vishwanath KELKAR, Michael ALTHAR
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Publication number: 20110134613Abstract: An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.Type: ApplicationFiled: December 7, 2010Publication date: June 9, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Zaki MOUSSAOUI, Nikhil Vishwanath KELKAR