Patents by Inventor Nikila Krishnamoorthy
Nikila Krishnamoorthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094284Abstract: Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.Type: ApplicationFiled: November 8, 2022Publication date: March 21, 2024Inventors: Tarun Kumar Goyal, Nikila Krishnamoorthy
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Patent number: 11879939Abstract: An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.Type: GrantFiled: February 8, 2022Date of Patent: January 23, 2024Assignee: NXP B.V.Inventors: Nikila Krishnamoorthy, Abhishek Mahajan, Rishabh Kaistha, Varsha Bansal
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Publication number: 20230251310Abstract: An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.Type: ApplicationFiled: February 8, 2022Publication date: August 10, 2023Inventors: Nikila Krishnamoorthy, Abhishek Mahajan, Rishabh Kaistha, Varsha Bansal
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Publication number: 20230213580Abstract: The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.Type: ApplicationFiled: January 5, 2022Publication date: July 6, 2023Inventors: Shikhar Makkar, Nikila Krishnamoorthy
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Patent number: 11686769Abstract: The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.Type: GrantFiled: January 5, 2022Date of Patent: June 27, 2023Assignee: NXP B.V.Inventors: Shikhar Makkar, Nikila Krishnamoorthy
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Patent number: 11144677Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.Type: GrantFiled: August 8, 2019Date of Patent: October 12, 2021Assignee: NXP USA, Inc.Inventors: Stefan Doll, Thomas Henry Luedeke, Nikila Krishnamoorthy, Hubert Glenn Carson, Jr., Anurag Jindal, Hilario Manuel Garza, Kamel Musa Khalaf, Joel Ray Knight, Adrian Lee Carleton
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Patent number: 10955473Abstract: A semiconductor device including scan configuration circuitry that reconfigures latches of the device into a scan chain in response to assertion of a scan enable control signal, and scan control circuitry including delay circuitry, scan enable circuitry, evaluation circuitry, and scan reset circuitry. The scan reset circuitry keeps each of the secure latches in a predetermined reset state until assertion of both an evaluation signal and a scan mode signal. The delay circuitry includes N series-coupled flip-flops selected from different cell libraries detecting assertion of the scan mode signal and asserting a delay output signal only after N transitions of a test clock. The scan enable circuitry asserts the scan enable control signal when a scan enable command signal and the delay output signal are both asserted. The evaluation circuitry asserts the evaluation signal only when a collective state of the delay circuitry has achieved a predetermined state.Type: GrantFiled: November 1, 2019Date of Patent: March 23, 2021Assignee: NXP B.V.Inventors: Sandeep Jain, Thomas E. Tkacik, Nikila Krishnamoorthy
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Publication number: 20210042447Abstract: A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Applicant: NXP USA, Inc.Inventors: Stefan Doll, Thomas Henry Luedeke, Nikila Krishnamoorthy, Hubert Glenn Carson, JR., Anurag Jindal, Hilario Manuel Garza, Kamel Musa Khalaf, Joel Ray Knight, Adrian Lee Carleton
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Patent number: 8458541Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.Type: GrantFiled: March 25, 2011Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Sandeep Jain, Nikila Krishnamoorthy, Abhishek Chaudhary, Nipun Mahajan, Saurabh Chauhan
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Publication number: 20120246531Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.Type: ApplicationFiled: March 25, 2011Publication date: September 27, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Sandeep Jain, Nikila Krishnamoorthy, Abhishek Chaudhary, Nipun Mahajan, Saurabh Chauhan
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Patent number: 7421634Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).Type: GrantFiled: June 15, 2005Date of Patent: September 2, 2008Assignee: Texas Instruments IncorporatedInventors: Naga Satya Srikanth Puvvada, Nikila Krishnamoorthy, Sandeep Jain, Jais Abraham
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Patent number: 7213184Abstract: Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.Type: GrantFiled: July 12, 2004Date of Patent: May 1, 2007Assignee: Texas Instruments IncorporatedInventors: Nikila Krishnamoorthy, Anindya Saha, Rubin Ajit Parekhji
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Patent number: 7134061Abstract: A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.Type: GrantFiled: December 9, 2003Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Anindya Saha, Rubin A. Parekhji
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Publication number: 20060248422Abstract: According to an aspect of present invention, modules designed to operate with different frequency in functional (normal) mode are tested using a sequential scan based technique at the respective frequencies. In one embodiment the interface logic connecting the two modules is tested for at-speed performance (i.e., the same speed at which the interface would be operated in functional mode during normal operation).Type: ApplicationFiled: June 15, 2005Publication date: November 2, 2006Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Naga Satya Puvvada, Nikila Krishnamoorthy, Sandeep Jain, Jais Abraham
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Patent number: 7120842Abstract: A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.Type: GrantFiled: September 22, 2003Date of Patent: October 10, 2006Assignee: Texas Instruments IncorporatedInventors: Gordhan Barevadia, Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Rubin Ajit Parekhji, Neil J. Simpson
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Patent number: 6925408Abstract: A mixed-signal core designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module. This type of partitioning enables the mixed-signal core to have three modes of operation, using which the analog, mixed-signal and digital components can all be tested.Type: GrantFiled: October 1, 2003Date of Patent: August 2, 2005Assignee: Texas Instruments IncorporatedInventors: Amit Premy, Vudutha V. N. Suresh Gupta, Anupama Aniruddha Agashe, Nikila Krishnamoorthy, Rubin A. Parekhji
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Publication number: 20050091562Abstract: Testing of modules (such as Intellectual property (IP) cores) in integrated circuits (such as system on a chip units (SOCs)) in situations when different modules operate with different characteristics of a control signal. In an embodiment, another module (“subsystem module”) may be implemented to be tested with any of a multiple characteristics of a control signal, and a register which is programmable to generate a derived control signal of a desired characteristic from an original control signal, is provided. The derived control signal is provided to test the subsystem module. According to an aspect of the invention the desired characteristic may be determined, for example, to test a path between the two modules at the same speed as at which the path would be operated in a functional mode.Type: ApplicationFiled: July 12, 2004Publication date: April 28, 2005Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Nikila KRISHNAMOORTHY, Anindya SAHA, Rubin PAREKHJI
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Publication number: 20050066243Abstract: A system and method enhance observability of IC failures during burn-in tests. Scan automatic test pattern generation and memory built-in self-test patterns are monitored during the burn-in tests to provide a mechanism for observing selective scan chain outputs and memory BIST status outputs.Type: ApplicationFiled: September 22, 2003Publication date: March 24, 2005Inventors: Gordhan Barevadia, Anupama Agashe, Nikila Krishnamoorthy, Rubin Parekhji, Neil Simpson
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Publication number: 20050065747Abstract: A mixed-signal core disclosed herein is designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module.Type: ApplicationFiled: October 1, 2003Publication date: March 24, 2005Inventors: Amit Premy, Vudutha Suresh Gupta, Anupama Agashe, Nikila Krishnamoorthy, Rubin Parekhji
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Publication number: 20050055615Abstract: A scan test circuitry design imbedded on an SoC having the scan architecture of a VLCT platform is disclosed herein. This BIST circuitry design that is not limited in the number of scan test ports supported includes at least one scan chain group having a corresponding clock domain that couples to receive test stimulus data. Each scan chain group has a corresponding test mode signal to shift the test stimulus data at a shift clock rate derived from its corresponding clock domain. A controlling demultiplexer connects to each multiplexer unit within each scan chain group to provide control signals for shifting in the test stimulus. A clock control mechanism provides a control signal for each scan chain to shift test stimulus and capture resultant data. Furthermore, when a simultaneous test mode signal is enabled, the clock control mechanism couples to each scan chain to enable simultaneous capture of each scan chain group.Type: ApplicationFiled: December 9, 2003Publication date: March 10, 2005Inventors: Anupama Agashe, Nikila Krishnamoorthy, Anlndya Saha, Rubin Parekhji