Patents by Inventor Nikita Naresh
Nikita Naresh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11852683Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.Type: GrantFiled: January 17, 2023Date of Patent: December 26, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh
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Publication number: 20230402124Abstract: A device including a controller coupled to memory components via a forward data path, and a signature register coupled to the memory components via a backward data path. The controller provides memory address signals and a controller clock signal to the memory components via the forward data path, which includes first circuitry to provide test-enable signals to the memory components that enable the memory components to read stored memory values. The backward data path includes second circuitry to receive from the memory components a set of memory signals and combine them into a combined signal. Each memory signal is associated with a respective one of the memory components and includes at least one stored memory value read from the corresponding memory component. The signature register calculates a test signature based on the combined signal and compares the test signature to an expected signature.Type: ApplicationFiled: August 22, 2023Publication date: December 14, 2023Inventors: Nitesh MISHRA, Nikita NARESH
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Patent number: 11776656Abstract: An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.Type: GrantFiled: November 30, 2021Date of Patent: October 3, 2023Assignee: Texas Instruments IncorporatedInventors: Nitesh Mishra, Nikita Naresh
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Patent number: 11715544Abstract: An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.Type: GrantFiled: November 30, 2021Date of Patent: August 1, 2023Assignee: Texas Instruments IncorporatedInventors: Nitesh Mishra, Nikita Naresh
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Patent number: 11680984Abstract: In some examples, a circuit includes a custom control data register (CCDR) circuit having a scan path. The CCDR circuit includes a shift register and an update register. The shift register is configured to receive scan data from a scan data input (CDR_SCAN_IN) on a first clock edge responsive to a scan enable signal (CDR_SCAN_EN) being enabled. The update register is configured to receive data from the shift register on a second clock edge after the first clock edge when the scan enable (CDR_SCAN_EN) is enabled. The update register data is asserted as a scan data output (CDR_SCAN_OUT). The second scan path includes the scan data input, the shift register, the update register, and the scan data output.Type: GrantFiled: February 28, 2022Date of Patent: June 20, 2023Assignee: Texas Instruments IncorporatedInventors: Wilson Pradeep, Aravinda Acharya, Nikita Naresh
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Publication number: 20230152373Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh
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Patent number: 11555853Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.Type: GrantFiled: November 10, 2020Date of Patent: January 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh
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Publication number: 20220415423Abstract: An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.Type: ApplicationFiled: November 30, 2021Publication date: December 29, 2022Inventors: Nitesh MISHRA, Nikita NARESH
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Patent number: 11521698Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.Type: GrantFiled: August 26, 2020Date of Patent: December 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh, Naveen Ambalametil Narayanan
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Publication number: 20220358230Abstract: Methods and apparatus are disclosed to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain that includes data storage elements and design logic coupled to the scan chain. The example apparatus also includes data storage to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.Type: ApplicationFiled: June 22, 2021Publication date: November 10, 2022Inventors: Prakash Narayanan, Nikita Naresh
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Publication number: 20220343995Abstract: An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.Type: ApplicationFiled: November 30, 2021Publication date: October 27, 2022Inventors: Nitesh MISHRA, Nikita NARESH
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Publication number: 20210055345Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.Type: ApplicationFiled: November 10, 2020Publication date: February 25, 2021Inventors: Prakash NARAYANAN, Nikita NARESH
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Patent number: 10866280Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.Type: GrantFiled: April 1, 2019Date of Patent: December 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh
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Publication number: 20200388346Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.Type: ApplicationFiled: August 26, 2020Publication date: December 10, 2020Inventors: Prakash NARAYANAN, Nikita NARESH, Prathyusha Teja INUGANTI, Rakesh Channabasappa YARADUYATHINAHALLI, Aravinda ACHARYA, Jasbir SINGH, Naveen Ambalametil NARAYANAN
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Patent number: 10818374Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.Type: GrantFiled: February 8, 2019Date of Patent: October 27, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh, Naveen Ambalametil Narayanan
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Publication number: 20200309851Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.Type: ApplicationFiled: April 1, 2019Publication date: October 1, 2020Inventors: Prakash NARAYANAN, Nikita NARESH
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Publication number: 20200135290Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.Type: ApplicationFiled: February 8, 2019Publication date: April 30, 2020Inventors: Prakash NARAYANAN, Nikita NARESH, Prathyusha Teja INUGANTI, Rakesh Channabasappa YARADUYATHINAHALLI, Aravinda ACHARYA, Jasbir SINGH, Naveen Ambalametil NARAYANAN
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Patent number: 10460821Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: GrantFiled: February 14, 2018Date of Patent: October 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Publication number: 20180174663Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Inventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra
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Patent number: 9899103Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.Type: GrantFiled: February 16, 2017Date of Patent: February 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Nikita Naresh, Vaskar Sarkar, Rajat Mehrotra