Patents by Inventor Nikka Ko

Nikka Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8648404
    Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nikka Ko, Katsunori Yahashi
  • Publication number: 20130032874
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile semiconductor memory device. The device includes a plurality of electrode films stacked along a first axis perpendicular to a major surface of a substrate, a plurality of semiconductor layers penetrating through the electrode films, and a memory film provided between the electrode films and the semiconductor layer. The method can include forming a first stacked body by alternately stacking a plurality of first films and second films. The method can include forming a support unit supporting the first films. The method can include forming a first hole and removing the second films via the first hole to form a second stacked body. The method can include forming a plurality of through holes penetrating through the first films. In addition, the method can include burying the memory film and the semiconductor layers in the through holes.
    Type: Application
    Filed: January 17, 2012
    Publication date: February 7, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Nikka KO
  • Publication number: 20120319173
    Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.
    Type: Application
    Filed: November 17, 2011
    Publication date: December 20, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nikka KO, Katsunori YAHASHI
  • Patent number: 8062940
    Abstract: A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell layer, thereby forming first wirings and separating the memory cell layer; burying a first interlayer film in the first trenches to form a stacked body; forming a second wiring layer above the stacked body; forming a plurality of second trenches, extending in a second direction intersecting the first direction and reaching an upper surface of the first interlayer film in depth, in the first stacked body with the second wiring layer formed thereabove, thereby forming second wirings; removing the first interlayer film isotropically; and digging the second trenches down to an upper surface of the first wirings, thereby forming memory cells.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nikka Ko, Tomoya Satonaka, Katsunori Yahashi
  • Publication number: 20110223769
    Abstract: According to one embodiment, a method of fabricating a semiconductor device, including, selectively forming a first film as a core member on a film to be processed, forming a second film on a side surface and an upper surface of the core member, and on an upper surface of the film to be processed to cover the film, the second film which is constituted with same material as the first film and is doped with impurities being different in amount from impurities in the first film, removing the second film on the core member and on the film to be processed to form a sidewall mask constituted with the second film on the side surface of the core member, selectively removing the core member, and etching the film to be processed using the sidewall mask film as a mask.
    Type: Application
    Filed: February 14, 2011
    Publication date: September 15, 2011
    Inventors: Nikka Ko, Katsunori Yahashi, Kei Hattori
  • Publication number: 20100176368
    Abstract: A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell layer, thereby forming first wirings and separating the memory cell layer; burying a first interlayer film in the first trenches to form a stacked body; forming a second wiring layer above the stacked body; forming a plurality of second trenches, extending in a second direction intersecting the first direction and reaching an upper surface of the first interlayer film in depth, in the first stacked body with the second wiring layer formed thereabove, thereby forming second wirings; removing the first interlayer film isotropically; and digging the second trenches down to an upper surface of the first wirings, thereby forming memory cells.
    Type: Application
    Filed: November 19, 2009
    Publication date: July 15, 2010
    Inventors: Nikka KO, Tomoya Satonaka, Katsunori Yahashi