Abstract: A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T?2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2?X?T, wherein, for each value of X in the range 1?X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

Abstract: Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Abstract: A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T?2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2?X?T, wherein, for each value of X in the range 1?X<T,: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.

Abstract: The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.

Abstract: The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

Abstract: The present invention relates to analogue-to-digital converter circuitry, and in particular to alignment between one set of analogue-to-digital circuitry and another set. Such sets may be referred to as converter channels.

Abstract: A non-linearity evaluation circuit for use with a signal generator having at least a partly non-linear operation. The non-linearity evaluation circuit may include a detection unit operable to detect a given amplitude attribute in a target signal generated by the signal generator, a time position of the amplitude attribute in the target signal defining a time location of a snapshot time window relative to the target signal, a part of the target signal occupying the snapshot time window being a corresponding signal snapshot, and a presence of the given amplitude attribute indicating that the signal snapshot includes noise due to the non-linear operation of the signal generator. The non-linearity evaluation circuit may further include a controller operable to analyse the signal snapshot rather than a larger part of the target signal and to evaluate the non-linear characteristics of the operation of the signal generator based on the analysis.

Abstract: The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.

Abstract: A non-linearity evaluation circuit for use with a signal generator having at least partly non-linear operation, the non-linearity evaluation circuit comprising: a detection unit operable to detect a given amplitude attribute in a target signal generated by the signal generator, the time position of the amplitude attribute in the target signal defining the time location of a snapshot time window relative to the target signal, the part of the target signal occupying the snapshot time window being a corresponding signal snapshot, and the presence of the given amplitude attribute indicating that the signal snapshot includes noise due to the non-linear operation of the signal generator; and a controller operable to analyse the signal snapshot rather than a larger part of the target signal and to evaluate the non-linear characteristics of the operation of the signal generator based on the analysis.

Abstract: The present invention relates to semiconductor integrated circuitry, and in particular to such circuitry where one or a plurality of similar or identical operating units are each operable to carry out an operation dependent on a reference signal. One example of such an operating unit is a sub-ADC unit of analogue-to-digital converter (ADC) circuitry, which employs one or more such sub-ADC units to convert samples of an input analogue signal into representation digital values. Where there are a plurality of sub-ADC units, they may each convert samples of an input analogue signal into representative digital values. They may also operate in a time-interleaved manner so that their conversion rate (from sample to digital value) can be lower than the overall sample rate by a factor of the number of sub-ADC units.

Abstract: The present invention relates to analogue-to-digital converter circuitry, and in particular to alignment between one set of analogue-to-digital circuitry and another set. Such sets may be referred to as converter channels.

Abstract: Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.

Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.

Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.

Abstract: Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.

Abstract: Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.