Abstract: Methods and systems for a variable system on demand are disclosed. Aspects of the method may include configuring one or more filters in a wireless transmitter and/or receiver for a desired band and standard. The presence of a blocker signal in a receiver may be known and/or determined and the receiver may be configured for mitigating the blocker signal. A desired received signal strength indicator may be compared to a wideband received signal strength indicator. Gain levels may be configured in the receiver based on the comparison. Linearity of the receiver may be configured for blocker signal mitigation. The filters may include baseband filters and/or may be at an output of the receiver. The filters may include a plurality of stages, with one or more of the stages bypassed for filter configuring, and may include a mixer as an input. Capacitors and/or resistors may be configured in the filters.

Abstract: Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.

Abstract: A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on a reference oscillation. The comparison module is coupled to compare the waveform with a plurality of references to produce a plurality of waveform comparisons. The clock signal module is coupled to generate a clock signal from the plurality of waveform comparisons.

Abstract: A clock circuit includes a waveform generator, a comparison module, and a clock signal module. The waveform generator is coupled to generate a waveform based on a reference oscillation. The comparison module is coupled to compare the waveform with a plurality of references to produce a plurality of waveform comparisons. The clock signal module is coupled to generate a clock signal from the plurality of waveform comparisons.

Abstract: A method and system for filter calibration using fractional-N frequency synthesized signals are presented. Aspects of the method may include generating an LO signal by a PLL circuit within a chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. A frequency response for a filter circuit integrated within the chip may be calibrated by adjusting parameters associated with the filter circuit based on the generated LO signal. Aspects of the system may include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The frequency response may be calibrated by adjusting the filter based on the generated reference signal.

Abstract: Aspects of a method and system for a multi-band direct conversion CMOS mobile television tuner are provided. A single-chip multi-band RF receiver in a mobile terminal comprising UHF and L-band front-ends receives and amplifies an RF signal utilizing an LNA integrated into the front-end that corresponds to the type of signal received. A received signal strength indicator (RSSI) value may be determined for the amplified signal within the single-chip receiver and may be utilized to adjust a gain of the LNA. The adjustment may be made via on-chip or off-chip processing of the RSSI value. The single-chip receiver may directly convert the amplified signal to a baseband frequency signal and generate in-phase and quadrature components. The components of the baseband frequency signal may be filtered and/or amplified via programmable devices within the single-chip receiver. Circuitry within the single-chip receiver may be controller via an on-chip digital interface.

Abstract: Aspects of a method and system for a fractional-N synthesizer for a mobile digital cellular television environment are presented. Aspects of the system may include circuitry, within a phase locked loop, that enables determination of a division number at a time instant within a division cycle. A local oscillator signal may be modified based on the division number in a succeeding division cycle. A subsequent local oscillator signal may be generated based on the modification.