Patents by Inventor Nikolaos L. Kanistras

Nikolaos L. Kanistras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9003257
    Abstract: The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 7, 2015
    Assignee: u-blox AG
    Inventors: Ahmed S Mahdi, Nikolaos L Kanistras, Vassilis Paliouras
  • Publication number: 20150082112
    Abstract: The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: Antcor S.A.
    Inventors: Ahmed S. Mahdi, Nikolaos L. Kanistras, Vassilis Paliouras
  • Patent number: 8930790
    Abstract: The present invention is directed toward identifying selected values from among a set of values. In accordance with an embodiment, a method of identifying two selected values from among a plurality of values comprises: partitioning the plurality of values into pairs of values; for each pair of values, using a comparator to select one of the two values to form a vector from the selected value of each pair; and applying the vector to a hardware unit that identifies first and second extreme values from among the values of the vector.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: January 6, 2015
    Assignee: u-blox AG
    Inventors: Ioannis Tsatsaragkos, Nikolaos L. Kanistras, Vassilis Paliouras