Patents by Inventor Nikolaos Mouravliansky

Nikolaos Mouravliansky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synthesis of DC accurate noise compatible reduced netlist
    Patent number: 10262094
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 16, 2019
    Assignee: Helic, Inc.
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky, Konstantis Daloukas
  • Synthesis of reduced netlist having positive elements and no controlled sources
    Patent number: 9672318
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 6, 2017
    Assignee: HELIC, INC.
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky
  • SYNTHESIS OF REDUCED NETLIST HAVING POSITIVE ELEMENTS AND NO CONTROLLED SOURCES
    Publication number: 20160378905
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky
  • SYNTHESIS OF DC ACCURATE NOISE COMPATIBLE REDUCED NETLIST
    Publication number: 20160378889
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky, Konstantis Daloukas