Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.

Abstract: A non-volatile programmable latch (110) in an integrated circuit (310) is initialized by an initialization signal (SET). At least a portion of the initialization signal is generated in response to a command to the circuit to perform a circuit initialization operation. In some embodiments, the circuit is a synchronous dynamic random access memory (SDRAM), or a synchronous graphics random access memory (SGRAM). The command is a mode register set command (MRS). The command is received when a predetermined period of time has elapsed after power was turned on. Waiting for the predetermined period of time before initializing the latch allows the voltage powering the latch to develop so that the latch can be initialized reliably.

Abstract: In a semiconductor dynamic random access memory, a single path data pipeline for applying voltages from a sense amplifier to a data output pad for different column address signal (CAS) latencies comprising: a dual input single output latch, the dual inputs coupled to data bit (S1) and data bit bar (S1) outputs of a sense amplifier and producing a single bit data output in response thereto, a buffer circuit coupled to the output latch and operable in response to enable signals (EN, EN) for passing the data output from the latch, a dual input multiplexer (mux) with each input having a circuit for receiving the data output from the buffer circuit, one input circuit including a delay circuit for delaying application of the data output from the buffer circuit to the mux, the mux operable in response to a column address (CAS) latency signal to pass one of two signals, and logic gates coupled to pass the mux output to control the application of a voltage to a data output pad.

Abstract: A decoder for use in addressing a spare column select line for use in a semiconductor random access memory includes a plurality of input lines each connected to a Y predecoder line, each input line including a pass gate for passing the bit connected thereto in response to an enable signal and a fuse link serially connected with a pass gate, a plurality of fuse links being connected in parallel to provide one of a first plurality of address inputs, a logic gate for receiving said first plurality of address inputs from said plurality of input lines and generating a spare column select signal, whereby all decoder pass gates are disabled until the spare word line is selected for use, the address for the spare line being defined by ablation of fuse links in unwanted Y predecoder lines.