Patents by Inventor Nikolay RYZHENKO

Nikolay RYZHENKO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240355819
    Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Quan SHI, Sukru YEMENICIOGLU, Marni NABORS, Nikolay RYZHENKO, Xinning WANG, Sivakumar VENKATARAMAN
  • Patent number: 12051692
    Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 30, 2024
    Assignee: Intel Corporation
    Inventors: Quan Shi, Sukru Yemenicioglu, Marni Nabors, Nikolay Ryzhenko, Xinning Wang, Sivakumar Venkataraman
  • Publication number: 20220262791
    Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.
    Type: Application
    Filed: February 16, 2021
    Publication date: August 18, 2022
    Inventors: Quan SHI, Sukru YEMENICIOGLU, Marni NABORS, Nikolay RYZHENKO, Xinning WANG, Sivakumar VENKATARAMAN