Patents by Inventor Nikolay Suetin

Nikolay Suetin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer with gel-based biochips for electrochemical synthesis and electrical detection of polymers
    Patent number: 10035147
    Abstract: An embodiment of the invention relates to a wafer comprising a plurality of biochips and interconnects on the wafer, the biochip comprising a biochip pad, a synthesis electrode and a gel comprising a probe, wherein a plurality of the biochip pads of the plurality of the biochips are interconnected by the interconnects to carry out a chemical reaction on a plurality of the synthesis electrodes.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Nikolay Suetin
  • GEL-BASED BIO CHIP FOR ELECTROCHEMICAL SYNTHESIS AND ELECTRICAL DETECTION OF POLYMERS
    Publication number: 20150231633
    Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.
    Type: Application
    Filed: December 31, 2014
    Publication date: August 20, 2015
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Gel-based bio chip for electrochemical synthesis and electrical detection of polymers
    Patent number: 8940143
    Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Increasing photoresist processing throughput
    Patent number: 8617784
    Abstract: Two acids may be formed per exposed photon using free radical promotion so that two acid products are produced via two parallel pathways. This results in increased fabrication facility throughput. In some embodiments, this may be achieved while reducing side-lobe defect liability.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: David Fryer, Vivek Singh, Nikolay Suetin, Alex A. Granovsky
  • ELECTROCHEMICAL SYNTHESIS AND ELECTRICAL DETECTION OF POLYMERS WITH GEL-BASED BIO CHIP
    Publication number: 20090000957
    Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Increasing photoresist processing throughput
    Publication number: 20070275323
    Abstract: Two acids may be formed per exposed photon using free radical promotion so that two acid products are produced via two parallel pathways. This results in increased fabrication facility throughput. In some embodiments, this may be achieved while reducing side-lobe defect liability.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 29, 2007
    Inventors: David Fryer, Vivek Singh, Nikolay Suetin, Alex A. Granovsky