Patents by Inventor Nikolay Vasilyuk

Nikolay Vasilyuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9164897
    Abstract: An architecture of a NAND Flash memory module interface controller (NAND-controller) provides access to data stored in an external NAND Flash memory module, and a method of booting firmware. NAND-controller automatically boots firmware from the NAND Flash memory into primary RAM of a system-on-a chip used for GNSS receivers. NAND-controller has a first external interface to connect NAND Flash memory, a second external interface to set parameters of booting firmware, and two internal interfaces: a high-speed one (system interface) and a low-speed one (control interface) to be connected to two types of SoC internal busses. Data exchange between the CPU and NAND Flash memory is implemented using a static RAM buffer which is a part of the NAND-controller and available for reading and writing via high-speed interface. Parameters of the first external interface are set and current state of data exchange process is controlled by the CPU.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: October 20, 2015
    Assignee: Topcon Positioning Systems, Inc.
    Inventor: Nikolay Vasilyuk
  • Publication number: 20150234742
    Abstract: An architecture of a NAND Flash memory module interface controller (NAND-controller) provides access to data stored in an external NAND Flash memory module, and a method of booting firmware. NAND-controller automatically boots firmware from the NAND Flash memory into primary RAM of a system-on-a chip used for GNSS receivers. NAND-controller has a first external interface to connect NAND Flash memory, a second external interface to set parameters of booting firmware, and two internal interfaces: a high-speed one (system interface) and a low-speed one (control interface) to be connected to two types of SoC internal busses. Data exchange between the CPU and NAND Flash memory is implemented using a static RAM buffer which is a part of the NAND-controller and available for reading and writing via high-speed interface. Parameters of the first external interface are set and current state of data exchange process is controlled by the CPU.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Applicant: TOPCON POSITIONING SYSTEMS, INC.
    Inventor: Nikolay Vasilyuk
  • Patent number: 9053015
    Abstract: An architecture of a NAND Flash memory module interface controller (NAND-controller) provides access to data stored in an external NAND Flash memory module, and a method of booting firmware. NAND-controller automatically boots firmware from the NAND Flash memory into primary RAM of a system-on-a chip used for GNSS receivers. NAND-controller has a first external interface to connect NAND Flash memory, a second external interface to set parameters of booting firmware, and two internal interfaces: a high-speed one (system interface) and a low-speed one (control interface) to be connected to two types of SoC internal busses. Data exchange between the CPU and NAND Flash memory is implemented using a static RAM buffer which is a part of the NAND-controller and available for reading and writing via high-speed interface. Parameters of the first external interface are set and current state of data exchange process is controlled by the CPU.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 9, 2015
    Assignee: Topcon Positioning Systems, Inc.
    Inventor: Nikolay Vasilyuk
  • Publication number: 20140372670
    Abstract: An architecture of a NAND Flash memory module interface controller (NAND-controller) provides access to data stored in an external NAND Flash memory module, and a method of booting firmware. NAND-controller automatically boots firmware from the NAND Flash memory into primary RAM of a system-on-a chip used for GNSS receivers. NAND-controller has a first external interface to connect NAND Flash memory, a second external interface to set parameters of booting firmware, and two internal interfaces: a high-speed one (system interface) and a low-speed one (control interface) to be connected to two types of SoC internal busses. Data exchange between the CPU and NAND Flash memory is implemented using a static RAM buffer which is a part of the NAND-controller and available for reading and writing via high-speed interface. Parameters of the first external interface are set and current state of data exchange process is controlled by the CPU.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Applicant: TOPCON POSITIONING SYSTEMS, INC.
    Inventor: Nikolay Vasilyuk