Abstract: A method for performing integrated circuit testing is presented. A compactor is generated using explicit expander graph construction. A decompressor and the generated compactor are inserted within a device-under-tested (DUT). After feeding a compressed test pattern into the DUT, the compressed test pattern is expanded via the decompressor into internal scan-ins within the DUT. Subsequently, the internal scan-out data is compressed into compressed output vectors using the generated compactor. After shifting out from the DUT, the compressed output vectors are compared to a set of desired outputs in order to determine a pass/fail status of the DUT.

Abstract: An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.