Patents by Inventor Niladri MOJUMDER
Niladri MOJUMDER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10591531Abstract: An apparatus is disclosed. The apparatus includes a circuit, a conductor interconnecting a portion of the circuit, and a processor configured to determine a temperature of the conductor and adjust at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The at least one parameter includes a lifetime estimate for the conductor. A method of operating an apparatus including a circuit and a conductor interconnecting a portion of the circuit is disclosed. The method includes determining a temperature of the conductor, and adjusting at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The parameter includes a lifetime estimate for the conductor.Type: GrantFiled: June 9, 2016Date of Patent: March 17, 2020Assignee: Qualcomm IncorporatedInventors: Rajit Chandra, Melika Roshandell, Niladri Mojumder
-
Publication number: 20180143853Abstract: A system includes a computer processor including N cores; and a plurality of device aging sensors, wherein each one of the plurality of device aging sensors is disposed within a respective core, the plurality of device aging sensors being configured to communicate core aging information with a core scheduler in the computer processor, wherein the core scheduler is configured to make a first set of M cores available to a thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a first time period in which the core aging information indicates that aging of the first set of M cores is below a threshold, and wherein the core scheduler is configured to make a second set of M cores available to the thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a second time period.Type: ApplicationFiled: January 5, 2017Publication date: May 24, 2018Inventors: Mehdi Saeidi, Niladri Mojumder, Min Chen, Rajat Mittal, Rajit Chandra
-
Patent number: 9666481Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.Type: GrantFiled: April 28, 2016Date of Patent: May 30, 2017Assignee: QUALCOMM IncorporatedInventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, Niladri Mojumder, Mustafa Badaroglu
-
Publication number: 20160363623Abstract: An apparatus is disclosed. The apparatus includes a circuit, a conductor interconnecting a portion of the circuit, and a processor configured to determine a temperature of the conductor and adjust at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The at least one parameter includes a lifetime estimate for the conductor. A method of operating an apparatus including a circuit and a conductor interconnecting a portion of the circuit is disclosed. The method includes determining a temperature of the conductor, and adjusting at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The parameter includes a lifetime estimate for the conductor.Type: ApplicationFiled: June 9, 2016Publication date: December 15, 2016Inventors: Rajit CHANDRA, Melika ROSHANDELL, Niladri MOJUMDER
-
Publication number: 20160240437Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.Type: ApplicationFiled: April 28, 2016Publication date: August 18, 2016Inventors: Stanley Seungchul SONG, Choh Fei YEAP, Zhongze WANG, Niladri MOJUMDER, Mustafa BADAROGLU
-
Patent number: 9349686Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.Type: GrantFiled: March 12, 2014Date of Patent: May 24, 2016Assignee: QUALCOMM INCORPORATEDInventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, Niladri Mojumder, Mustafa Badaroglu
-
Patent number: 9336864Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.Type: GrantFiled: August 29, 2014Date of Patent: May 10, 2016Assignee: QUALCOMM IncorporatedInventors: Niladri Mojumder, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
-
Patent number: 9318564Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.Type: GrantFiled: May 19, 2014Date of Patent: April 19, 2016Assignee: QUALCOMM IncorporatedInventors: Niladri Mojumder, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
-
Publication number: 20160064068Abstract: A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Niladri Mojumder, Stanley Seungchul Song, Zhongze Wang, Choh Fei Yeap
-
Publication number: 20150333131Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: QUALCOMM IncorporatedInventors: Niladri MOJUMDER, Stanley Seungchul SONG, Zhongze WANG, Choh Fei YEAP
-
Publication number: 20150262930Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Applicant: QUALCOMM IncorporatedInventors: Stanley Seungchul SONG, Choh Fei YEAP, Zhongze WANG, Niladri MOJUMDER, Mustafa BADAROGLU
-
Patent number: 8966418Abstract: An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices.Type: GrantFiled: March 15, 2013Date of Patent: February 24, 2015Assignee: Globalfoundries Inc.Inventors: Niladri Mojumder, Bipul Paul, Anurag Mittal, Werner Juengling
-
Publication number: 20140282330Abstract: An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Niladri MOJUMDER, Bipul Paul, Anurag Mittal, Juengling Werner