Patents by Inventor Nilanjan Chatterjee

Nilanjan Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9449133
    Abstract: Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: September 20, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Hua Xue, Mohan Tandyala, Nilanjan Chatterjee, Venkatesan Rajappan
  • Patent number: 9390210
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: July 12, 2016
    Assignee: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Nilanjan Chatterjee, Venkatesan Rajappan, Mohan Tandyala
  • Publication number: 20150347642
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.
    Type: Application
    Filed: October 8, 2014
    Publication date: December 3, 2015
    Applicant: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Nilanjan Chatterjee, Venkatesan Rajappan, Mohan Tandyala
  • Publication number: 20150324509
    Abstract: Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.
    Type: Application
    Filed: May 7, 2014
    Publication date: November 12, 2015
    Applicant: Lattice Semiconductor Corporation
    Inventors: Hua Xue, Mohan Tandyala, Nilanjan Chatterjee, Venkatesen Rajappan
  • Patent number: 7800404
    Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: September 21, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Hare K Verma, Manoj Gunwani, Conrad Kong, Jai Liu, Nilanjan Chatterjee
  • Publication number: 20090160483
    Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 25, 2009
    Inventors: Hare K. Verma, Manoj Gunwani, Conrad Kong, Jai Liu, Nilanjan Chatterjee