Patents by Inventor Nilashis Dey

Nilashis Dey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11853134
    Abstract: Example implementations relate to a fluid cooling assembly for a computing system, and a tool-less method of installing the fluid cooling assembly to the computing system. The fluid cooling assembly includes a plurality of cooling components, and a fluid chamber having a plurality of first fluid connectors. Further, each cooling component includes a plurality of second fluid connectors. Each first fluid connector or each second fluid connector includes a first end to protrude beyond a first surface of a circuit board of the computing system, and a second end to protrude beyond a second surface of the circuit board. Further, the first end of each first fluid connector is connected to the first end of a respective second fluid connector via the circuit board, to establish a parallel fluid flow path between the fluid chamber and each of the plurality of cooling components.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: December 26, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent W. Michna, David S. Chialastri, Nilashis Dey, Yasir Jamal
  • Publication number: 20230359256
    Abstract: A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.
    Type: Application
    Filed: June 7, 2023
    Publication date: November 9, 2023
    Inventors: David Scott Chialastri, Vincent W. Michna, Nilashis Dey, Yasir Jamal
  • Patent number: 11709529
    Abstract: A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: July 25, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: David Scott Chialastri, Vincent W. Michna, Nilashis Dey, Yasir Jamal
  • Patent number: 11644879
    Abstract: Example implementations relate to a power control system for controlling transmission of power from one or more power supply devices to one or more loads of a modular server enclosure. The power control system includes an electronic fuse and a threshold control unit. The electronic fuse is connected between one or more loads and the one or more power supply devices of the modular server enclosure. The threshold control unit is connected to the electronic fuse and to the one or more power supply devices. The threshold control circuit dynamically adjusts a threshold current for the electronic fuse based on a power supply capacity of the one or more power supply devices. The electronic fuse controls the transmission of the power from the one or more power supply devices to the one or more loads based on threshold current and a load current drawn by the one or more loads.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: May 9, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent W. Michna, Nilashis Dey
  • Publication number: 20230114466
    Abstract: Example implementations relate to a fluid cooling assembly for a computing system, and a tool-less method of installing the fluid cooling assembly to the computing system. The fluid cooling assembly includes a plurality of cooling components, and a fluid chamber having a plurality of first fluid connectors. Further, each cooling component includes a plurality of second fluid connectors. Each first fluid connector or each second fluid connector includes a first end to protrude beyond a first surface of a circuit board of the computing system, and a second end to protrude beyond a second surface of the circuit board. Further, the first end of each first fluid connector is connected to the first end of a respective second fluid connector via the circuit board, to establish a parallel fluid flow path between the fluid chamber and each of the plurality of cooling components.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Vincent W. Michna, David S. Chialastri, Nilashis Dey, Yasir Jamal
  • Publication number: 20230109810
    Abstract: A compute device may include one or more processors operable at variable performance levels depending upon power supplied from a compute device power supply. A baseboard management controller of the compute device may periodically calculate an adjustment value for the power supply to adjust the power delivered to the one or more processors. The adjustment value may be calculated as a function of a thermal margin between the temperature of the one or more processors over time and a thermal operating limit of the one or more processors.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: David Scott Chialastri, Vincent W. Michna, Nilashis Dey, Yasir Jamal
  • Publication number: 20230074993
    Abstract: Example implementations relate to a power control system for controlling transmission of power from one or more power supply devices to one or more loads of a modular server enclosure. The power control system includes an electronic fuse and a threshold control unit. The electronic fuse is connected between one or more loads and the one or more power supply devices of the modular server enclosure. The threshold control unit is connected to the electronic fuse and to the one or more power supply devices. The threshold control circuit dynamically adjusts a threshold current for the electronic fuse based on a power supply capacity of the one or more power supply devices. The electronic fuse controls the transmission of the power from the one or more power supply devices to the one or more loads based on threshold current and a load current drawn by the one or more loads.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Vincent W. Michna, Nilashis Dey
  • Patent number: 11304344
    Abstract: A device that is communicating with other devices via a common bus discovers addresses of the other devices. The device transmits data to the other devices at a transmit time determined based on the addresses of the other devices. The device predicts receive times at which data will be received from the other devices and determines the transmit time based on predicted receive times, avoiding data collisions. The devices may include universal sensor data acquisition devices (“USDADs”) that are each connectable to different types of sensors arranged within a server rack. Each USDAD determines a type of a connected sensor that is within a server rack and collects sensor data from the connected sensor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 12, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nilashis Dey, Peter Hansen
  • Patent number: 11289857
    Abstract: An example electrical connector includes a magnetic core embedded in the overmold and encircling conductive paths therein and a Hall-effect sensor embedded in the overmold and configured to sense a magnetic field of the magnetic core. The Hall-effect sensor generates an output that indicates whether or not the supply current flowing through the connector matches the return current flowing through the connector, and this output may be used to detect stray-current faults in which current bypasses the connector to return via alternative paths such as through a device chassis. The connector may include one or more supply wires embedded in the overmold, one or more return wires embedded in the overmold, one or more supply terminals embedded in the overmold and terminating the supply wires, and one or more return terminals embedded in the overmold and terminating the return wires.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 29, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nilashis Dey, Vincent W. Michna, Patrick Raymond
  • Patent number: 11102149
    Abstract: Switches and groups of IO ports may be divided into separate switch modules and IO modules that can be connected by high-speed low-loss management cables in a variety of configurations. Thereafter, the separate modules may be replaced independently of each other. The switch module may recognize, and thereafter ignore, unconnected ports, removing the performance penalty that sometimes arises when fewer than all available ports are connected. The switch module may rapidly adjust to addition, subtraction, and replacement of connected IO modules.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 24, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Nilashis Dey, John M. Lenthall, David A. Selvidge, Minh Nguyen
  • Publication number: 20210194826
    Abstract: Switches and groups of IO ports, conventionally integrated on a single shared PCB, may be divided into separate switch modules and IO modules that can be connected by high-speed low-loss management cables in a variety of configurations. Thereafter, the separate modules may be replaced independently of each other. Some of the management connections may be parallel, similar to production-data connections. Alternatively, a series of IO modules (e.g., a chain or a ring) may be managed by a single switch module using a management method. The management method may include collecting and updating configuration and status information specific to each of the IO modules and, by extension, each of their IO ports. This enables the switch module to recognize, and thereafter ignore, unconnected ports, removing the performance penalty that sometimes arises when fewer than all available ports are connected. It also allows the switch module to rapidly adjust to addition, subtraction, and replacement of connected IO modules.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Nilashis Dey, John M. Lenthall, David A. Selvidge, Minh Nguyen
  • Publication number: 20210037680
    Abstract: A device that is communicating with other devices via a common bus discovers addresses of the other devices. The device transmits data to the other devices at a transmit time determined based on the addresses of the other devices. The device predicts receive times at which data will be received from the other devices and determines the transmit time based on predicted receive times, avoiding data collisions. The devices may include universal sensor data acquisition devices (“USDADs”) that are each connectable to different types of sensors arranged within a server rack. Each USDAD determines a type of a connected sensor that is within a server rack and collects sensor data from the connected sensor.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Nilashis Dey, Peter Hansen
  • Patent number: 10881017
    Abstract: Examples described herein include a backplane keying mechanism. The backplane keying mechanism may include a backplane, a first connector, a second connector, a first block for the first connector, and a second block for the second connector. The first block and the second block may be moveable as one unit on the backplane from a first state to a second state. In the first state, the first block allows the first connect to connect to a first type of device and the second block allows the second connector to connect to the first type of device. In the second state, the first block prohibits the first connector from connecting to the first type of device and the second block prohibits the second connector from connecting to the first type of device.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent W. Michna, Nilashis Dey, Charles Cornwell, David Chialastri
  • Publication number: 20200313365
    Abstract: An example electrical connector includes a magnetic core embedded in the overmold and encircling conductive paths therein and a Hall-effect sensor embedded in the overmold and configured to sense a magnetic field of the magnetic core. The Hall-effect sensor generates an output that indicates whether or not the supply current flowing through the connector matches the return current flowing through the connector, and this output may be used to detect stray-current faults in which current bypasses the connector to return via alternative paths such as through a device chassis. The connector may include one or more supply wires embedded in the overmold, one or more return wires embedded in the overmold, one or more supply terminals embedded in the overmold and terminating the supply wires, and one or more return terminals embedded in the overmold and terminating the return wires.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Nilashis Dey, Vincent W. Michna, Patrick Raymond
  • Patent number: 10785874
    Abstract: A technique includes coupling a resistor network to a plurality of card edge connectors. The resistor network has a resistance, and each card edge connector includes electrical contacts to couple a resistor of a circuit card assembly, when inserted into the card edge connector, to the resistor network to alter the resistance of the resistor network. The technique includes determining a state of the plurality of card edge connectors based on a signal that is provided by the resistor network.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Nilashis Dey
  • Publication number: 20200245503
    Abstract: A method for balancing air flow impedance within an enclosure. The method includes determining a configuration of each hardware module of a plurality of hardware modules arranged in a housing of the enclosure. The method also includes determining impedance settings for a plurality of adjustable air flow impedance elements within the housing, based at least in part on the configurations of the plurality of hardware modules, that will balance air flow impedances of the plurality of hardware modules. The method further includes setting the plurality of adjustable air flow impedance elements according to the determined impedance settings.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Inventors: David Chialastri, Travis J. Gaskill, Vincent W. Michna, Nilashis Dey, Patrick Raymond
  • Publication number: 20200229306
    Abstract: A technique includes coupling a resistor network to a plurality of card edge connectors. The resistor network has a resistance, and each card edge connector includes electrical contacts to couple a resistor of a circuit card assembly, when inserted into the card edge connector, to the resistor network to alter the resistance of the resistor network. The technique includes determining a state of the plurality of card edge connectors based on a signal that is provided by the resistor network.
    Type: Application
    Filed: January 11, 2019
    Publication date: July 16, 2020
    Inventor: Nilashis Dey
  • Publication number: 20200100380
    Abstract: Examples described herein include a backplane keying mechanism. The backplane keying mechanism may include a backplane, a first connector, a second connector, a first block for the first connector, and a second block for the second connector. The first block and the second block may be moveable as one unit on the backplane from a first state to a second state. In the first state, the first block allows the first connect to connect to a first type of device and the second block allows the second connector to connect to the first type of device. In the second state, the first block prohibits the first connector from connecting to the first type of device and the second block prohibits the second connector from connecting to the first type of device.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Vincent W. Michna, Nilashis Dey, Charles Cornwell, David Chialastri
  • Patent number: 10554580
    Abstract: Examples disclosed herein relate to fabric cable emulation. Some examples disclosed herein include determining connection data associated with a connection between a fabric interface of a cluster node in a fabric cluster and a fabric switch. Based on the determined connection data, configuration parameters for the connection may be calculated and stored in a memory device on the cluster node. An interface signal may be asserted to the fabric interface of the cluster node after the calculated configuration parameters are stored to indicate that the cluster node is available in the fabric cluster.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Nilashis Dey, Peter Hansen, John M. Lenthall
  • Publication number: 20180152394
    Abstract: Examples disclosed herein relate to fabric cable emulation. Some examples disclosed herein include determining connection data associated with a connection between a fabric interface of a cluster node in a fabric cluster and a fabric switch. Based on the determined connection data, configuration parameters for the connection may be calculated and stored in a memory device on the cluster node. An interface signal may be asserted to the fabric interface of the cluster node after the calculated configuration parameters are stored to indicate that the cluster node is available in the fabric cluster.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Inventors: Melvin K. Benedict, Nilashis Dey, Peter Hansen, John M. Lenthall