Patents by Inventor Nilesh Gharia

Nilesh Gharia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583166
    Abstract: A memory cell comprises a dual-gate fin field effect transistor (FinFET) and first and second serially connected magnetic tunnel junction (MTJ) devices for improving reliability of memory operations. The FinFET represents an access transistor and includes a first gate and a second gate. The second gate is configured to be electrically independent from the first gate and to adjust threshold voltage of the FinFET. Each of the first and second MTJ devices represent a magnetic storage element and includes at least two ferromagnetic (FM) layers separated by a thin insulating layer forming a tunneling junction. Based on the relative magnetization of the two FM layers, each MTJ device has high and low resistance states. Higher reliability of memory write operation is primarily achieved with the help of FinFET and higher reliability of memory read operation is primarily achieved with increased read margin.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 28, 2017
    Assignee: Broadcom Corporation
    Inventor: Nilesh Gharia
  • Publication number: 20140340958
    Abstract: A memory cell comprises a dual-gate fin field effect transistor (FinFET) and first and second serially connected magnetic tunnel junction (MTJ) devices for improving reliability of memory operations. The FinFET represents an access transistor and includes a first gate and a second gate. The second gate is configured to be electrically independent from the first gate and to adjust threshold voltage of the FinFET. Each of the first and second MTJ devices represent a magnetic storage element and includes at least two ferromagnetic (FM) layers separated by a thin insulating layer forming a tunneling junction. Based on the relative magnetization of the two FM layers, each MTJ device has high and low resistance states. Higher reliability of memory write operation is primarily achieved with the help of FinFET and higher reliability of memory read operation is primarily achieved with increased read margin.
    Type: Application
    Filed: June 14, 2013
    Publication date: November 20, 2014
    Inventor: Nilesh GHARIA
  • Publication number: 20050262295
    Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.
    Type: Application
    Filed: June 15, 2005
    Publication date: November 24, 2005
    Inventors: Bindiganavale Nataraj, Nilesh Gharia, Rupesh Roy, Jose Pereira, Varadarajan Srinivasan, Sandeep Khanna, Hok Wong