Abstract: A system and method for improved evaluation of semiconductor hardware is provided. The system comprises a firmware repository server, which firmware repository server comprises a plurality of firmware packages for the one or more evaluation hardware boards. The firmware repository server is further configured to: receive a firmware request for a user evaluation hardware board from a first of the client devices, search the plurality of firmware packages for compatible firmware packages for the user evaluation hardware board, generate a catalog of the compatible firmware packages for the user evaluation hardware board, transmit the catalog to the first client device, receive a request for a user selected firmware package from the catalog of compatible firmware packages, and to transmit firmware of the user selected firmware package to the client device for installation on the user evaluation hardware board.

Abstract: A system and method for improved evaluation of semiconductor hardware is provided. The system comprises a firmware repository server, which firmware repository server comprises a plurality of firmware packages for the one or more evaluation hardware boards. The firmware repository server is further configured to: receive a firmware request for a user evaluation hardware board from a first of the client devices, search the plurality of firmware packages for compatible firmware packages for the user evaluation hardware board, generate a catalog of the compatible firmware packages for the user evaluation hardware board, transmit the catalog to the first client device, receive a request for a user selected firmware package from the catalog of compatible firmware packages, and to transmit firmware of the user selected firmware package to the client device for installation on the user evaluation hardware board.

Abstract: Sensorless driving of a brushless DC (BLDC) motor includes detecting a zero crossing time from back electromotive force (BEMF) voltage of the BLDC motor. An instantaneous BEMF voltage and an average BEMF voltage are compared to detect the crossover time, which can be used to change the commutation switching sequence. Since the average BEMF voltage differs for odd and even steps of the commutation switching sequence, average BEMF voltages are calculated separately for odd and even sequences and compared to instantaneous BEMF voltages to detect crossover points for the odd and even sequences. The times to commutations for the odd and even sequences are averaged to provide an average time to the next commutation cycle. The average time can be scaled by a reduction factor to reduce the effects of measurement noise.

Abstract: Sensorless driving of a brushless DC (BLDC) motor includes detecting a zero crossing time from back electromotive force (BEMF) voltage of the BLDC motor. An instantaneous BEMF voltage and an average BEMF voltage are compared to detect the crossover time, which can be used to change the commutation switching sequence. Since the average BEMF voltage differs for odd and even steps of the commutation switching sequence, average BEMF voltages are calculated separately for odd and even sequences and compared to instantaneous BEMF voltages to detect crossover points for the odd and even sequences. The times to commutations for the odd and even sequences are averaged to provide an average time to the next commutation cycle. The average time can be scaled by a reduction factor to reduce the effects of measurement noise.

Abstract: A direct memory access controller has a data register for transferring data from a source to a destination address. A pattern register is provided and a data comparator is coupled with the data register and the pattern register for comparing the content of the data register with the content of the pattern register. A control unit coupled with the comparator controls the data flow and stops a data transfer if the comparator detects a match of the data register and the pattern register.

Abstract: A direct memory access (DMA) controller may comprise a DMA bus, a memory coupled to the DMA bus, a DMA engine coupled with the DMA bus, a cyclic redundancy check (CRC) module coupled with the DMA engine, and a bus interface coupled to the DMA engine and the CRC module.

Abstract: A direct memory access controller may comprise a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled with the data register and the pattern register, and a control unit coupled with the comparator operable to stop a data transfer if the comparator detects a match of the data register and the pattern register.

Abstract: The invention is a carrier comprising three support elements connected by an underlying frame. The periphery of a wafer rests upon the support elements. The invention also comprises a wafer handler with a plurality of arms. Spacers space the carrier above a base plate associated with a station in a wafer handling area. An arm slides beneath the frame and between the spacers, but the handler does not contact the wafer. A method of using the handler and carrier is provided where the handler lifts and rotates the carrier with the wafer through various stations in a wafer handling area. A control device reduces the handler speed only at critical points of the processing cycle. The handler is capable of moving a plurality of carriers and wafers simultaneously.