Patents by Inventor Nilesh Shah

Nilesh Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030176478
    Abstract: The invention provides non-steroidal ligands for the glucocorticoid receptor, methods for making non-steroidal ligands of the glucocorticoid receptor, compositions of non-steroidal ligands of the glucocorticoid receptor and methods of using non-steroidal ligands and compositions of non-steroidal ligands of the glucocorticoid receptor for treating or preventing diseases (e.g., obesity, diabetes, depression, neurodegeneration or an inflammatory disease) associated with glucocorticoid binding to the glucocorticoid receptor.
    Type: Application
    Filed: January 22, 2003
    Publication date: September 18, 2003
    Inventors: Thomas S. Scanlan, Nilesh Shah
  • Publication number: 20030037127
    Abstract: A storage server in a storage area network (SAN) environment connecting host computers and storage devices. The storage server includes a plurality of storage processors and a switching circuit. Data is routed between the storage processors via the switching circuit according to routing tags. The routing tags are examined prior to completely receiving the data, allowing the data to be routed with minimal delay.
    Type: Application
    Filed: February 13, 2002
    Publication date: February 20, 2003
    Applicant: Confluence Networks, Inc.
    Inventors: Nilesh Shah, Rahim Ibrahim, Nghiep Tran, Tuan Nguyen
  • Patent number: 6026455
    Abstract: A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: February 15, 2000
    Assignee: Intel Corporation
    Inventors: Nilesh Shah, James Coke, Jasmin Ajanovic, Dahmane Dahmani, Rajeev Prasad
  • Patent number: 5777034
    Abstract: The invention encompasses a new methacrylate resin blend composition, and a method of making the blend composition, having improved solvent craze resistance. The new blend composition contains a methacrylate matrix resin, particles of a single layer polymer, and, optionally, an acrylic multi-layer polymer. Particles of the single layer polymer derived from 50% or more methyl methacrylate, and having weight average molecular weight (Mw) at least 120% of the Mw of the methacrylate matrix resin component of the blend, the particles having a diameter of from 50 to 500 nanometers, have been discovered to confer a solvent craze resistance value to the methacrylate resin blend which is at least twice the solvent craze resistance value of the methacrylate resin absent particles of the single layer polymer. Solvent craze resistance of the blend may be improved by as much as 10-fold or more over the solvent craze resistance of the methacrylate matrix resin alone.
    Type: Grant
    Filed: November 8, 1996
    Date of Patent: July 7, 1998
    Assignee: Rohm and Haas Company
    Inventors: Nilesh Shah, Manhua Lin
  • Patent number: 5761450
    Abstract: A bridge circuit adapted to be associated with a first faster bus circuit and a second slower bus circuit which bridge circuit includes a first path for transferring data between the first and second buses including a plurality of individual buffers each capable of storing a plurality of separately addressed increments of data destined for a plurality of sequential addresses, apparatus for storing data in the buffers at addresses provided by a bus master on the second bus, apparatus for detecting when data in a buffer is ready to be transferred to the first bus, apparatus for flushing any buffer which contains data ready to be transferred to the first bus, and apparatus for transferring data from the second bus to another of the plurality of buffers when a first buffer contains data ready to be transferred to the first bus until all of the buffers contain data ready to be transferred to the first bus
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: June 2, 1998
    Assignee: Intel Corporation
    Inventor: Nilesh Shah
  • Patent number: 5664117
    Abstract: A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.
    Type: Grant
    Filed: January 20, 1996
    Date of Patent: September 2, 1997
    Assignee: Intel Corporation
    Inventors: Nilesh Shah, Jasmin Ajanovic, Dahmane Dahmani
  • Patent number: 5535341
    Abstract: A bridge circuit adapted to be associated with first and second bus circuits which bridge circuit includes a first path including a plurality of buffers for storing data or addresses being transferred from the second bus to the first bus, a circuit arrangement for detecting that an interrupt of a presenting-running operation has occurred, a circuit arrangement for determining the state of the plurality of buffers when an interrupt occurs, and apparatus for flushing only those buffers of the plurality which were storing data for transfer when the interrupt occurred.
    Type: Grant
    Filed: February 24, 1994
    Date of Patent: July 9, 1996
    Assignee: Intel Corporation
    Inventors: Nilesh Shah, Rajeev Prasad