Patents by Inventor Nili Segal

Nili Segal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10586014
    Abstract: A method for combining verification data may include using a processor, obtaining verification data and a verification model from each of a plurality of verification engines relating to different verification methods, the verification data relating to a plurality of verification tests that were conducted on a design under test (DUT) using the plurality of verification engines; using a processor, merging the verification models obtained from the plurality of verification engines into a merged verification model; using a processor, calculating a combined verification metric grade for a plurality of verification entities in the merged verification model using verification metric grades for each of the plurality of verification entities calculated from the verification data obtained from the plurality of engines and applying a combined verification metric grade rule; and outputting the combined verification metric grade via an output device.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: March 10, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yael Kinderman, David Spatafore, Nili Segal, Yan Yagudayev, Vincent Reynolds
  • Patent number: 9824175
    Abstract: A method for automatically verifying validity of application of a refinement rule includes calculating a set of values that characterize a hierarchy of elements of the emulation. A currently calculated value for a first element at a first level of the hierarchy is compared with a previously calculated value that characterized the first element at a previous time. If the currently calculated value is the same as the previously calculated value, application of the refinement rule is determined to be valid for unnamed entities of the first element. If the currently calculated value is different from the previously calculated value, each currently calculated value that characterizes a lower level element at a lower level of the hierarchy is compared with a corresponding previously calculated value to identify a change and it is determined whether the change invalidates application of the refinement rule to an unnamed entity of the emulation.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 21, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hemant Gupta, Nili Segal, Yael Kinderman, Oded Oren
  • Patent number: 9582620
    Abstract: A computer implemented method and system for exclusion of entities from a metric driven verification analysis score. The method includes using a processor, and performing the following steps: parsing a source code simulating a device under test and modeling the source code into a model that includes entities of one or a plurality of metric driven entity types; identifying in the source code entities of the same metric driven entity type of said one or a plurality of metric driven entity types that are logically linked and saving information on the identified entities that are logically linked; receiving from a user a selection of an entity to be excluded from the metric driven verification analysis score; and excluding all instances of the selected entity and all instances of the identified entities that are logically linked to the selected entity from a calculation of the metric driven verification score.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: February 28, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Nili Segal, Yael Kinderman, Hemant Gupta, Oded Oren