Abstract: Thermal energy battery, comprising: an evaporator-condenser thermal energy storage (ec-TES), with an end for vapor and an end for liquid, comprising one-phase stationary material storing at least 70% of the thermal energy stored within the ec-TES, a storage tank for vapor and liquid (ST), with a vapor part at a higher elevation and a liquid part at a lower elevation, a vapor line, arranged to the vapor end of the ec-TES, for inlet and outlet of vapor, a liquid line arranged between the liquid end of the ec-TES and the liquid part of the ST, a tank vapor line arranged from the vapor part of the ST to the vapor line or the vapor end of the ec-TES, and an evaporation control valve (CV6) in the tank vapor line.

Abstract: Thermal energy battery, comprising: an evaporator-condenser thermal energy storage (ec-TES), with an end for vapor and an end for liquid, comprising one-phase stationary material storing at least 70% of the thermal energy stored within the ec-TES, a storage tank for vapor and liquid (ST), with a vapor part at a higher elevation and a liquid part at a lower elevation, a vapor line, arranged to the vapor end of the ec-TES, for inlet and outlet of vapor, a liquid line arranged between the liquid end of the ec-TES and the liquid part of the ST, a tank vapor line arranged from the vapor part of the ST to the vapor line or the vapor end of the ec-TES, and an evaporation control valve (CV6) in the tank vapor line.

Abstract: Thermal energy storage—TES—comprising: at least two blocks or zones operated with respect to charging and discharging of thermal energy by flowing a heat transfer fluid—HTF—through the block or zone; an inlet charging manifold; an outlet charging manifold; an inlet pipe arranged from the inlet charging manifold to each block or zone; an outlet from each block or zone; and further structure as follows: one or more of the valves: a flow control valve (Vi1; Va1, . . . Ve1) arranged in at least one of block or zone inlet pipes, inlets, outlets and outlet pipes, for control of flow through the block or zone; a bypass valve (Vi2; Va2, . . . Ve2) arranged in inlet charging side pipe sections between inlet pipe and serial flow return for the block or zone, for bypassing flow and serial flow control; and an outlet charging side switch valve (Vis; Vas, . . .

Abstract: A high temperature thermal energy storage includes a foundation comprising thermal insulation, at least one self-supported cassette arranged on the foundation. At least one cassette is a self-supporting frame or assembled structure with respect to transport and installation, containing a number of concrete thermal energy storage elements, some or all of the elements include heat exchangers embedded in the concrete of the elements. A pipe system includes an inlet and an outlet for thermal input to and output from the storage, respectively. The pipe system is fluidly coupled to the heat exchangers for circulating fluid through the heat exchangers for thermal energy input to or output from the elements and thermal insulation around and on top of the at least one self-supported cassette containing concrete thermal energy storage elements.

Abstract: High temperature thermal energy storage, distinctive in that the storage comprises: a thermally insulated foundation, at least one self-supported cassette arranged on said foundation, which cassette is a self-supporting frame or structure containing a number of concrete thermal energy storage elements, some or all of said elements comprising embedded heat exchangers, a pipe system, the pipe system comprising an inlet and an outlet for thermal input to and output from the storage, respectively, and connections to said heat exchangers for circulating fluid through said heat exchangers for thermal energy input to or output from said thermal energy storage elements, and thermal insulation around and on top of the at least one self-supported cassette with concrete thermal storage elements. The invention also provides a method of building and methods of operating the storage.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: A metal inter-diffusion bonding method for forming hermetically sealed wafer-level packaging for MEMS devices. A stack of a first metal is provided on a surface of both a first wafer and a second wafer, the first metal being susceptible to oxidation in air; providing a layer of a second metal, having a melting point lower than that of the first metal, on an upper surface of each stack of the first metal, the layer of second metal being sufficiently thick to inhibit oxidation of the upper surface of the first metal; bringing the layer of the second metal on the first wafer into contact with the layer of second metal on the second wafer to form a bond interface; and applying a bonding pressure to the first and second wafers at a bonding temperature lower than the melting point of the second metal to initiate a bond, the bonding pressure being sufficient to deform the layers of the second metal at the bond interface.

Abstract: A micro-electromechanical device or MEMS having a conformal layer of material deposited by atomic layer deposition is discussed. The layer may provide physical protection to moving components of the device, may insulate electrical components of the device, may present a biocompatible surface interface to a biological system, and may otherwise improve such devices. The layer may also comprise a combination of multiple materials each deposited with great control to allow creating layers of customizable properties and to allow creating layers having multiple independent functions, such as providing physical protection from wear and providing electrical insulation.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: Integrated circuit-chip hot spot temperatures are reduced by providing localized regions of higher thermal conductivity in the conductive material interface at pre-designed locations by controlling how particles in the thermal paste stack- or pile-up during the pressing or squeezing of excess material from the interface. Nested channels are used to efficiently decrease the thermal resistance in the interface, by both allowing for the thermally conductive material with a higher particle volumetric fill to be used and by creating localized regions of densely packed particles between two surfaces.

Abstract: Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

Abstract: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.