Abstract: A packet data switch for transferring data packets including an address part and an information part from one of a plurality of incoming data links (10,30,50) to one or more outgoing data links (22, 42, 62) and supplying new address information for each data packet on the outgoing links. The selector includes a separate memory means (e.g. 13) for each incoming data link (10, 30, 50) and a separate memory means (e.g. 20) for each outgoing data link (22, 42, 62). The memory means assigned to the incoming data links send control signals for selective writing of a data packet into one or more buffer registers (e.g. 19) which are each assigned to an outgoing link (e.g. 22). The memory means assigned to the outgoing links supply the new address information for the data packets to the outgoing links.