Abstract: A system and method for supporting tracking of data values of original source code at execution of a translated target version of the source code on a computer system. The system associates references to target data value containers in the target code with corresponding address information of original data value containers of the source code during program code translation. The system also stores, at execution of the target code, information related to target code instructions together with associated address information of original data value containers of the source code to uphold a data value view of the original source code.

Abstract: The read latency caused by job start preparation of a future job is at least partly hidden within the current job by reading information for job start preparation of the future job integrated with the execution of the current job. Instructions for job start preparation are preferably instrumented (701) into the current job and executed (702), whenever possible, in parallel with the instructions of the current job. The integrated job start preparation may include table look-ups, register file updating, instruction fetching and preparation. If the scheduled job order is allowed to change during execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution of the next job and take appropriate actions (704; 705, 706) depending on the outcome of the test.

Abstract: he invention concerns the general data value problem, and especially the residence problem in a computer system when executing program code translated from a source code representation (10) into a target code representation (30). A basic idea of the invention is to associate references to target data value containers (40) in the target code with corresponding address information of original data value containers (20) of the source code during program code translation, and store information related to target code instructions together with associated address information of original data value containers at execution of target code to uphold a data value view (50) of the original source code representation. In this way, tracking of data values of original source code (10) at execution of translated target code (30) in a target system is supported in a highly efficient manner.

Abstract: A processor (PR2) has a functional unit (FU21) connected to series coupled temporary registers (TR21-TR23) and to a register file (RF2), which has an output connected to an input (IP1) of the functional unit via multiplexors (MUX1-MUX4). Read addresses (B, E, A) and write addresses (A, D, G) are sent to the register file and to a control means. The latter includes registers (REG1-REG4) and comparators (C1-C4) which control the multiplexors (MUX1-MUX4). On a read address (B) a value (V(B)) is sent to the functional unit (FU21) after the register file access time has lapsed. The functional unit performs an operation and the result (V(A)) is clocked through the temporary registers (TR1-TR3) and is sent to the register file (RF2). A later read address (A) coincides in the comparator (C2) with a write address (A) from the register (REG2), the multiplexer (MUX2) is switched and the result (V(A)) is fetched from the temporary register (TR1).

Abstract: The invention is directed toward a multiprocessing system having multiple processing units. For at least one of the processing units in the multiprocessing system, a first job signal is assigned to the processing unit for speculative execution of a corresponding first job, and a further job signal is assigned to the processing unit for speculative execution of a corresponding further job. The speculative execution of said further job is initiated when the processing unit has completed execution of the first job. If desirable, even more job signals may be assigned to the processing unit for speculative execution. In this way, multiple job signals are assigned to the processing units of the processing system, and the processing units are allowed to execute a plurality of jobs speculatively while waiting for commit priority.

Abstract: A problem in a message-based pipelined processor system is that the pipelining features of the execution pipeline of the system can not be fully utilized when the first stages of the pipeline are awaiting the determination of a memory address by the last stage of the pipeline. The invention therefore proposes that the message-based memory addresses are determined before the messages are buffered, or even earlier, already at message sending, so that the memory addresses are ready for use as soon as message processing by the pipeline is intiated. This typically means that the address determination routine of the operating system is executed, and that the corresponding memory address is included in the relevant message before the message is buffered in the message buffers. In this way, the memory address can be loaded into the program counter and the instructions fetched right away as soon as message processing is initiated.