Abstract: An optical device includes a waveguide slab, first and second input port couplers, and first and second output port couplers located over a planar optical substrate. The waveguide slab has a plane of symmetry. The first and second input port couplers extend from the waveguide slab and have an input coupler pair axis located about midway between the first and second input port couplers. The input coupler pair axis is offset at a nonzero first distance from the plane of symmetry. The first and second output port couplers extend from the waveguide slab and have an output coupler pair axis located about midway between the first and second output port couplers. The output coupler pair axis is offset at a different nonzero second distance from the plane of symmetry.

Abstract: An optical device includes a waveguide slab, first and second input port couplers, and first and second output port couplers located over a planar optical substrate. The waveguide slab has a plane of symmetry. The first and second input port couplers extend from the waveguide slab and have an input coupler pair axis located about midway between the first and second input port couplers. The input coupler pair axis is offset at a nonzero first distance from the plane of symmetry. The first and second output port couplers extend from the waveguide slab and have an output coupler pair axis located about midway between the first and second output port couplers. The output coupler pair axis is offset at a different nonzero second distance from the plane of symmetry.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: A method for manufacturing an electronic-photonic device. Epitaxially depositing an n-doped III-V composite semiconductor alloy buffer layer on a crystalline surface of a substrate at a first temperature. Forming an active layer on the n-doped III-V epitaxial composite semiconductor alloy buffer layer at a second temperature, the active layer including a plurality of spheroid-shaped quantum dots. Depositing a p-doped III-V composite semiconductor alloy capping layer on the active layer at a third temperature. The second temperature is less than the first temperature and the third temperature. The active layer has a photoluminescence intensity emission peak in the telecommunication C-band.

Abstract: An optical integrated circuit comprises a semiconductor body, a semiconductor optical waveguide located on the body, and a bipolar phototransistor located on and optically coupled to the waveguide. In a preferred embodiment, the base region of the transistor is configured to absorb radiation propagating in the waveguide, but the emitter and collector regions are both configured not to absorb the propagating radiation. In a further preferred embodiment, the waveguide is configured to guide the radiation along a propagation axis therein, and the transistor makes an elongated footprint along the waveguide, the footprint being elongated along the direction of the propagation axis. In another preferred embodiment, the footprint is at least three times longer along the propagation axis than along a direction perpendicular thereto.

Abstract: Apparatus comprising: a first compound semiconductor composition layer doped to have a first charge carrier polarity; a second compound semiconductor composition layer doped to have a second charge carrier polarity and located on the first layer; a third compound semiconductor composition layer doped to have the first charge carrier polarity and located on the second layer; a base electrode on the second layer; and a spacer ring interposed between and defining a charge carrier access path distance between the base electrode and the third layer, the path distance being within a range of between about 200 ? and about 1000 ?. Techniques for making apparatus. Apparatus is useful as a heterobipolar transistor, particularly for high frequency applications.

Abstract: A method for fabricating a bipolar transistor includes forming collector, base, and emitter semiconductor layers on a substrate such that the layers form a vertical sequence with respect to an adjacent surface of the substrate. The method includes etching away a portion of a top one of the semiconductor layers to expose a portion of the base semiconductor layer and then, growing semiconductor on the exposed portion of the base layer. The top one of the semiconductor layers is the layer of the sequence that is located farthest from the substrate. The growing causes grown semiconductor to laterally surround a vertical portion of the top one of the semiconductor layers.