Abstract: Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed to. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

Abstract: Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

Abstract: A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge.

Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

Abstract: Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.

Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

Abstract: A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

Abstract: The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.

Abstract: Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells'threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

Abstract: Features within an integrated-circuit memory chip enables scrambling or randomization of data stored in an array of nonvolatile memory cells. In one embodiment, randomization within each page helps to control source loading errors during sensing and floating gate to floating gate coupling among neighboring cells. Randomization from page to page helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. In another embodiment, randomization is implemented both within a page and between pages. The scrambling or randomization may be predetermined, or code generated pseudo randomization or user driven randomization in different embodiments. These features are accomplished within the limited resource and budget of the integrated-circuit memory chip.

Abstract: Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element.

Abstract: In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.

Abstract: A data structure for a memory device is provided. The device includes an array having a plurality of rows of storage elements divided into logical units composed of a plurality of data structures. The data structure includes a data sector including user data and user attribute data. The user attribute data includes error correction coding (ECC) for the user data. The user attribute data includes information for other sectors in the logical unit. The data sector is provided in one of the plurality of rows having a higher degree of data integrity than others of said plurality of rows.

Abstract: Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula.

Abstract: A method of storing memory device data overhead information in data cells in a row of cells, the row being one of a plurality of rows comprising a unit of data, is disclosed. The method includes storing user data attribute information in an overhead portion of a data sector in the row adjacent to a portion of the data sector storing user data. Data attributes for user data in data sectors in other rows is stored in the overhead portion of the data sector, said row having greater user data integrity than others of said rows.