Abstract: An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full.

Abstract: An apparatus having first and second circuits is disclosed. The first circuit may be disposed on a first side of a bus and configured to store thresholds in a first memory. Each threshold generally represents a respective one of a plurality of regular bit patterns in first data. The first circuit may also be configured to generate second data by representing each respective first data as (i) an index to one of the thresholds and (ii) a difference between the one threshold and the respective first data. A width of the bus may be narrower than the respective first data. The second circuit may be disposed on a second side of the bus and configured to (i) store the thresholds and a plurality of items in a second memory and (ii) reconstruct the first data by adding the respective thresholds to the second data in response to the items.

Abstract: An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.

Abstract: An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition.

Abstract: An apparatus having first and second circuits is disclosed. The first circuit may be disposed on a first side of a bus and configured to store thresholds in a first memory. Each threshold generally represents a respective one of a plurality of regular bit patterns in first data. The first circuit may also be configured to generate second data by representing each respective first data as (i) an index to one of the thresholds and (ii) a difference between the one threshold and the respective first data. A width of the bus may be narrower than the respective first data. The second circuit may be disposed on a second side of the bus and configured to (i) store the thresholds and a plurality of items in a second memory and (ii) reconstruct the first data by adding the respective thresholds to the second data in response to the items.

Abstract: An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full.

Abstract: A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.

Abstract: A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and configured to provide request signals, priority signals and counter value signals representing current values of the counters at a given time and (2) a grant control unit coupled to the channel interfaces and configured to grant DMA access to one of the channel interfaces based on values of the priority signals and the counter value signals.