Patents by Inventor Nimrod Hermesh
Nimrod Hermesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11675534Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.Type: GrantFiled: October 20, 2022Date of Patent: June 13, 2023Assignee: Western Digital Technologies, Inc.Inventors: Julian Vlaiko, Idan Alrod, Tien-Chien Kuo, Nimrod Hermesh, Eran Sharon
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Patent number: 11646085Abstract: A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a pull-down resistor selectively coupled to the signal path via a second switch; and ODT control circuitry configured to enable ODT at the interface circuitry by causing each of the switches to be closed during a first stage of the read operation, and disable ODT at the interface circuitry by causing each of the switches to be open during a final stage of the read operation.Type: GrantFiled: June 17, 2021Date of Patent: May 9, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Evgeny Vigdorchik, Nimrod Hermesh
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Publication number: 20230043050Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.Type: ApplicationFiled: October 20, 2022Publication date: February 9, 2023Applicant: Western Digital Technologies, Inc.Inventors: Julian VLAIKO, Idan ALROD, Tien-Chien KUO, Nimrod HERMESH, Eran SHARON
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Publication number: 20220406387Abstract: A data storage system includes a plurality of memory dies and interface circuitry, including a receiver configured to receive pulses of a read clock signal; an I/O contact pad coupled to the receiver via a signal path of an interface channel; and on-die-termination (ODT) circuitry coupled to the I/O contact pad and the receiver. The ODT circuitry includes a plurality of resistor pairs, each including a pull-up resistor selectively coupled to the signal path via a first switch, and a pull-down resistor selectively coupled to the signal path via a second switch; and ODT control circuitry configured to enable ODT at the interface circuitry by causing each of the switches to be closed during a first stage of the read operation, and disable ODT at the interface circuitry by causing each of the switches to be open during a final stage of the read operation.Type: ApplicationFiled: June 17, 2021Publication date: December 22, 2022Applicant: SANDISK TECHNOLOGIES LLCInventors: Evgeny Vigdorchik, Nimrod Hermesh
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Publication number: 20220357882Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.Type: ApplicationFiled: May 7, 2021Publication date: November 10, 2022Inventors: Julian VLAIKO, Idan ALROD, Tien-Chien KUO, Nimrod HERMESH, Eran SHARON
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Patent number: 11494126Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a command, such as from a host device, to write data to the memory device, perform toggle mode (TM) encoding on the data, and send the TM encoded data to the memory device. The memory device is configured to receive the TM encoded data, decode the TM encoded data, and write the decoded data to a location within the memory device. The memory device is further configured to receive a read command to read data from a location within the memory device, read the data, TM encode the data, and send the TM encoded data to the controller. The controller is configured to receive and decode the TM encoded data, and send the decoded data to a host device.Type: GrantFiled: May 7, 2021Date of Patent: November 8, 2022Assignee: Western Digital Technologies, Inc.Inventors: Julian Vlaiko, Idan Alrod, Tien-Chien Kuo, Nimrod Hermesh, Eran Sharon
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Patent number: 10283200Abstract: An apparatus may include a controller configured to communicate with a plurality of dies via a signal path. The controller may notify the dies of its desire to communicate with a target die. In response, the dies may set on-die termination resistances of two or more of the dies to a low resistance value, which in turn may set an overall termination resistance of the memory dies to be lower than the low resistance value. The lower overall termination resistance may be closer to a characteristic impedance of a portion of the signal path comprising packaging components of a packaging of the dies compared to the low resistance value, thereby reducing impedance mismatch between the characteristic impedance of the packaging components and the termination resistance.Type: GrantFiled: September 10, 2018Date of Patent: May 7, 2019Assignee: SanDisk Technologies LLCInventors: Nimrod Hermesh, Eliran Kanza
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Publication number: 20190043578Abstract: An apparatus may include a controller configured to communicate with a plurality of dies via a signal path. The controller may notify the dies of its desire to communicate with a target die. In response, the dies may set on-die termination resistances of two or more of the dies to a low resistance value, which in turn may set an overall termination resistance of the memory dies to be lower than the low resistance value. The lower overall termination resistance may be closer to a characteristic impedance of a portion of the signal path comprising packaging components of a packaging of the dies compared to the low resistance value, thereby reducing impedance mismatch between the characteristic impedance of the packaging components and the termination resistance.Type: ApplicationFiled: September 10, 2018Publication date: February 7, 2019Applicant: SanDisk Technologies LLCInventors: Nimrod Hermesh, Eliran Kanza
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Publication number: 20180261286Abstract: An apparatus may include a controller configured to communicate with a plurality of dies via a signal path. The controller may notify the dies of its desire to communicate with a target die. In response, the dies may set on-die termination resistances of two or more of the dies to a low resistance value, which in turn may set an overall termination resistance of the memory dies to be lower than the low resistance value. The lower overall termination resistance may be closer to a characteristic impedance of a portion of the signal path comprising packaging components of a packaging of the dies compared to the low resistance value, thereby reducing impedance mismatch between the characteristic impedance of the packaging components and the termination resistance.Type: ApplicationFiled: March 8, 2017Publication date: September 13, 2018Applicant: SanDisk Technologies LLCInventors: Nimrod Hermesh, Eliran Kanza
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Patent number: 10074423Abstract: An apparatus may include a controller configured to communicate with a plurality of dies via a signal path. The controller may notify the dies of its desire to communicate with a target die. In response, the dies may set on-die termination resistances of two or more of the dies to a low resistance value, which in turn may set an overall termination resistance of the memory dies to be lower than the low resistance value. The lower overall termination resistance may be closer to a characteristic impedance of a portion of the signal path comprising packaging components of a packaging of the dies compared to the low resistance value, thereby reducing impedance mismatch between the characteristic impedance of the packaging components and the termination resistance.Type: GrantFiled: March 8, 2017Date of Patent: September 11, 2018Assignee: SanDisk Technologies LLCInventors: Nimrod Hermesh, Eliran Kanza