Patents by Inventor Nina Biddle
Nina Biddle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12588145Abstract: A method includes providing a layer of non-conductive material having a conductive electroplating seed layer formed on a surface thereof; applying a photoresist layer over the surface of the conductive electroplating seed layer; and defining wiring channels in the photoresist resist layer. The method includes electroplating a conductive material in the defined wiring channels; adhering a non-conductive layer over the photoresist layer and the plated conductive material in the wiring channels; and removing the layer of non-conductive material and the conductive electroplating seed layer.Type: GrantFiled: July 19, 2022Date of Patent: March 24, 2026Assignee: Microchip Technology Caldicot LimitedInventors: John Adam Tracy deMercleden Smithells, Nina Biddle
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Publication number: 20240276637Abstract: A method by attaching a component to a first PCB, positioning a prepreg, having a via hole and a component cavity, proximate the first PCB with the component in the component cavity, putting a conductive material in the via hole of the prepreg, positioning a second PCB proximate the first PCB with the component and prepreg between the first PCB and the second PCB, and curing the conductive material to form a sintered via connecting the first PCB with the second PCB. A device with a first PCB, a component attached to the first PCB, a second PCB proximate the first PCB with the component between the first PCB and the second PCB, and a sintered metal via of conductive material connecting the first PCB with the second PCB.Type: ApplicationFiled: July 7, 2023Publication date: August 15, 2024Applicant: Microchip Technology Caldicot LimitedInventors: George Taylor, Nina Biddle, Piers Tremlett
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Patent number: 11538732Abstract: A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.Type: GrantFiled: October 4, 2021Date of Patent: December 27, 2022Assignee: MICROCHIP TECHNOLOGY CALDICOT LIMITEDInventors: Philip Andrew Swire, Nina Biddle
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Publication number: 20220361329Abstract: A method includes providing a layer of non-conductive material having a conductive electroplating seed layer formed on a surface thereof; applying a photoresist layer over the surface of the conductive electroplating seed layer; and defining wiring channels in the photoresist resist layer. The method includes electroplating a conductive material in the defined wiring channels; adhering a non-conductive layer over the photoresist layer and the plated conductive material in the wiring channels; and removing the layer of non-conductive material and the conductive electroplating seed layer.Type: ApplicationFiled: July 19, 2022Publication date: November 10, 2022Applicant: Microchip Technology Caldicot LimitedInventors: John Adam Tracy deMercleden Smithells, Nina Biddle
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Patent number: 11488888Abstract: A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a circuit board, a semiconductor die electrically coupled to the circuit board and a Chemical Vapor Deposition Diamond (CVDD) coated wire. A portion of the CVDD-coated wire extends between a hot-spot on the semiconductor die and the circuit board. The board assembly includes a layer of thermally conductive paste that is disposed between the hot-spot on the semiconductor die and the circuit board. The layer of thermally conductive paste is in direct contact with a portion of the CVDD-coated wire.Type: GrantFiled: December 24, 2019Date of Patent: November 1, 2022Assignee: MICROCHIP TECHNOLOGY CALDICOT LIMITEDInventors: Philip Andrew Swire, Nina Biddle
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Patent number: 11432402Abstract: A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces.Type: GrantFiled: November 12, 2018Date of Patent: August 30, 2022Assignee: Microchip Technology Caldicot LimitedInventors: John Adam Tracy deMercleden Smithells, Nina Biddle
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Publication number: 20220028753Abstract: A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Applicant: Microchip Technology Caldicot LimitedInventors: Philip Andrew Swire, Nina Biddle
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Patent number: 11189543Abstract: A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a first circuit board having an opening extending through the first circuit board. A Chemical Vapor Deposition Diamond (CVDD) window extends within the opening. A layer of thermally conductive paste extends over the CVDD window. A semiconductor die extends over the layer of thermally conductive paste such that a hot-spot on the semiconductor die overlies the CVDD window.Type: GrantFiled: September 12, 2019Date of Patent: November 30, 2021Assignee: Microchip Technology Caldicot LimitedInventors: Philip Andrew Swire, Nina Biddle
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Publication number: 20210143080Abstract: A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a circuit board, a semiconductor die electrically coupled to the circuit board and a Chemical Vapor Deposition Diamond (CVDD) coated wire. A portion of the CVDD-coated wire extends between a hot-spot on the semiconductor die and the circuit board. The board assembly includes a layer of thermally conductive paste that is disposed between the hot-spot on the semiconductor die and the circuit board. The layer of thermally conductive paste is in direct contact with a portion of the CVDD-coated wire.Type: ApplicationFiled: December 24, 2019Publication date: May 13, 2021Applicant: Microsemi Semiconductor LimitedInventors: Philip Andrew Swire, Nina Biddle
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Publication number: 20210092842Abstract: A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer.Type: ApplicationFiled: November 12, 2018Publication date: March 25, 2021Applicant: Microsemi Semiconductor LimitedInventors: John Adam Tracy deMercleden Smithells, Nina Biddle
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Publication number: 20210035883Abstract: A method and apparatus for conducting heat away from a semiconductor die are disclosed. A board assembly is disclosed that includes a first circuit board having an opening extending through the first circuit board. A Chemical Vapor Deposition Diamond (CVDD) window extends within the opening. A layer of thermally conductive paste extends over the CVDD window. A semiconductor die extends over the layer of thermally conductive paste such that a hot-spot on the semiconductor die overlies the CVDD window.Type: ApplicationFiled: September 12, 2019Publication date: February 4, 2021Applicant: Microsemi Semiconductor LimitedInventors: Philip Andrew Swire, Nina Biddle
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Publication number: 20200120797Abstract: A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer.Type: ApplicationFiled: November 12, 2018Publication date: April 16, 2020Applicant: Microsemi Semiconductor LimitedInventors: John Adam Tracy deMercleden Smithells, Nina Biddle