Patents by Inventor Ning Ge

Ning Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SUBSTANCE DETECTION DEVICE
    Publication number: 20180284027
    Abstract: In an example implementation, a substance detection device includes a substrate having nanoimprinted chamber walls and nanostructures. The chamber walls define a chamber and the nanostructures are positioned within the chamber to react to a substance introduced into the chamber. A two-dimensional (2D) orifice plate is affixed to the chamber walls and forms a top side of the chamber.
    Type: Application
    Filed: November 13, 2015
    Publication date: October 4, 2018
    Inventors: Ning GE, Steven Barcelo, Charles M Santori, Helen A Holder
  • FOCAL ADJUSTMENT FOR ANALYTE DETECTION PACKAGE
    Publication number: 20180275065
    Abstract: An analyte detection system includes an analyte detection package to be presented to a reading device, and a focus mechanism to adjust a focal point of the analyte detection package relative to the reading device, with the analyte detection package including a surface-enhanced luminescence analyte stage, the reading device including optics to receive scattered radiation emitted luminescence from the analyte stage, and the focus mechanism to adjust the focal point relative to the optics.
    Type: Application
    Filed: January 29, 2016
    Publication date: September 27, 2018
    Inventors: Anita Rogacs, Viktor Shkolnikov, Ning Ge
  • SUBSTANCE DETECTION
    Publication number: 20180275066
    Abstract: In an example implementation, a substance detection method includes sensing for fluid in a chamber of a substance detection device. When fluid is sensed in the chamber, the method includes sensing again for fluid in the chamber. When no fluid is sensed in the chamber, the method includes initiating a substance detection process.
    Type: Application
    Filed: November 13, 2015
    Publication date: September 27, 2018
    Inventors: Ning GE, Steven Barcelo, Anita Rogacs, Helen A. Holder
  • NANO WIRE MICROPOROUS STRUCTURE
    Publication number: 20180272284
    Abstract: A microporous structure includes an array of nano wires and a coating about the nano wires of the array. The coating defines pores between the nano wires.
    Type: Application
    Filed: October 22, 2015
    Publication date: September 27, 2018
    Inventors: Steven Barcedo, Ning Ge, Anita Rogacs
  • Semiconductor device comprising a gate formed from a gate ring
    Patent number: 10084062
    Abstract: In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: September 25, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Leong Yap Chia, Pin Chin Lee, Jose Jehrome Rando
  • Addressing an EPROM
    Patent number: 10081178
    Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 25, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Leong Yap Chia, Wai Mun Wong
  • Ink level sensing
    Patent number: 10082414
    Abstract: In some examples, an ink level sensor includes a sense capacitor between a first node and ground, a first switch to couple a first voltage to the first node and charge the sense capacitor, a second switch to couple the first node with a second node and share the charge between the sense capacitor and a reference capacitor, causing a second voltage at the second node, and a transistor having a drain, a gate coupled to the second node, and a source coupled to ground, the transistor to provide a drain to source resistance in proportion to the second voltage.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 25, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Trudy Benjamin, Teck-Khim Neo, Joseph M. Torgerson, Neel Banerjee, George H. Corrigan, III
  • SPLIT MEMORY BANK
    Publication number: 20180268905
    Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
    Type: Application
    Filed: May 22, 2018
    Publication date: September 20, 2018
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
  • Integrated circuit devices comprising memristors
    Patent number: 10076904
    Abstract: In some examples, an integrated circuit device includes a substrate, a memristor over the substrate and comprising a first metal layer as a first electrode, a second metal layer as a second electrode, and a switching oxide layer between the first and second metal layers, and a thermal resistor layer over the substrate.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 18, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Jianhua Yang, Ning Ge, Zhiyong Li
  • Sensing a property of a fluid
    Patent number: 10071552
    Abstract: In an example, a device for sensing a property of a fluid may include an ion-sensitive field effect transistor (ISFET) having a gate, a source, and a drain. The device may also include a first metal element in contact with the gate and a switching layer in contact with the first metal layer. A resistance state of the switching layer is to be modified through application of an electrical field of at least a predefined strength through the switching layer and is to be retained in the switching layer following removal of the electrical field. The device may also include a metal plate in contact with the switching layer, in which the metal plate is to directly contact the fluid for which the property is to be sensed.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 11, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Zhiyong Li, Leong Yap Chia, Wai Mun Wong
  • Generating a representative logic indicator of grouped memristors
    Patent number: 10056142
    Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 21, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, R. Stanley Williams
  • ELECTRICALLY-FUNCTIONAL OPTICAL TARGET
    Publication number: 20180222188
    Abstract: In one example, a printhead having an electrically-functional optical target. The printhead includes a substrate. An optical target having an optically-distinguishable shape and formed from at least one polysilicon strip is deposited on the substrate. An electrical connection to at least one of the polysilicon strips connect the strip into a circuit that is deposited on the substrate.
    Type: Application
    Filed: October 30, 2015
    Publication date: August 9, 2018
    Inventors: Ning Ge, Ser Chia Koh, Chaw Sing Ho, John Patrick Oliver
  • Pre-charge line routed over pre-charge transistor
    Patent number: 10029457
    Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing cell, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: July 24, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
  • Selector relaxation time reduction
    Patent number: 10026477
    Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: July 17, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jianhua Yang, Ning Ge, John Paul Strachan, Gary Gibson, Warren Jackson
  • Bi-polar memristor
    Patent number: 10026476
    Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 17, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Leong Yap Chia, Ning Ge, Wai Mun Wong
  • Memristors with oxide switching layers
    Patent number: 10026894
    Abstract: An example memristor includes a first conductive layer, a switching layer, and a second conductive layer. The first conductive layer may include a first conductive material and a second conductive material. The second conductive material may have a higher diffusivity than the first conductive material. The switching layer may be coupled to the first conductive layer and may include a first oxide having the first conductive material and a second oxide having the second conductive material. The second conductive layer may be coupled to the switching layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 17, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, Minxian Zhang, Katy Samuels
  • Split memory bank
    Patent number: 10014055
    Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: July 3, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
  • Memristive cross-bar array for determining a dot product
    Patent number: 10008264
    Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: June 26, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ning Ge, Jianhua Yang, John Paul Strachan, Miao Hu
  • Printhead with a number of memristors and inverters
    Patent number: 9987842
    Abstract: A print head with a number of memristors and inverters is described. The print head includes a number of nozzles to deposit an amount of fluid onto a print medium. Each nozzle includes a firing chamber to hold the amount of fluid, an opening to dispense the amount of fluid onto the print medium, and an ejector to eject the amount of fluid through the opening. The print head also includes a number of memristor cells. Each memristor cell includes a memristor to store data, a voltage divider serially connected to the 116 memristor cell, and an inverter connected in parallel with the number of memristor cells and the voltage divider.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 5, 2018
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianwen Luo, Leong Yap Chia, Ning Ge
  • ADDRESSING AN EPROM
    Publication number: 20180147839
    Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Leong Yap Chia, Wai Mun Wong