Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.

Abstract: A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.

Abstract: Disclosed are a Media Access Control (MAC) address synchronization method, a switch, a Multi-Chassis Link Aggregation Group (MC-LAG) system, and a storage medium. The method may include: comparing a number of dynamic MAC addresses in the first device with a first preset threshold to obtain a first comparison result; adjusting the number of the dynamic MAC addresses in the first device according to the first comparison result; synchronizing the first device with the second device; comparing a sum of a number of dynamic MAC addresses in the second device and a number of static MAC addresses in the second device with a second preset threshold to obtain a second comparison result; adjusting the number of the dynamic MAC addresses in the second device according to the second comparison result; and synchronizing the first device with the second device.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate fin and a second substrate fin extending in a first direction, a first isolation strip extending in the first direction and spaced apart from the first substrate fin and the second substrate fin, a first source/drain structure on the first substrate fin, and a second source/drain structure on the second substrate fin. The first isolation strip is sandwiched between and in contact with a first sidewall of the first source/drain structure and a first sidewall of the second source/drain structure.

Abstract: A method for making a semiconductor device includes: forming a first semiconductor fin structure and a second semiconductor fin structure over a substrate that both extend along a first lateral direction; forming a dummy gate structure that extends along a second lateral direction perpendicular to the first direction and straddles the first and second semiconductor fin structures; removing a portion of the dummy gate structure between the first and second semiconductor fin structures to form a trench, a width of the trench along the second direction decreasing with increasing depth toward the substrate; filling the trench with a dielectric material; and removing the second semiconductor fin structure and a portion of the dielectric material.

Abstract: A central rearview mirror includes a profile-shaped mirror housing. The front of the mirror housing is provided with a first sliding chute, and a lens is slidably embedded in the first sliding chute. An end cover is removably installed at each of the two side ends of the mirror housing. The advantages of the central rearview mirror are as follows: The profile is adopted as the main body of the mirror housing, that is, the mirror housing is a solid straight bar with a certain cross-section shape so that each cross-section of the mirror housing is unified. When it is required to design central rearview mirrors of different lengths, it is only necessary to cut a large-length profile to obtain the mirror housing in the required length without tedious computer numerical control (CNC) processing or new mould-opening, thus reducing the production cost of the central rearview mirror.

Abstract: The method comprises: a first terminal displays an object on a display of the first terminal. The first terminal receives a drag operation entered by a user. The drag operation is used to initiate drag for the object. The first terminal displays, on the display of the first terminal in response to the drag operation, an animation in which the object moves with the drag operation. The first terminal sends drag data to a second terminal after determining that a drag intent of the user is cross-device drag. The drag data is used by the second terminal to display the object on a display of the second terminal.

Abstract: The present invention relates to a system for coordinating operation control and operation maintenance for an urban rail transit and a method using the same, where the system includes: an intelligent operation maintenance subsystem and an intelligent operation control subsystem, the intelligent operation maintenance subsystem and the intelligent operation control subsystem include coordination linkage engine modules respectively, and the intelligent operation maintenance subsystem synchronizes, by using the coordination linkage engine modules, a fault handling plan to the intelligent operation control subsystem. Compared with the prior art, the present invention has the advantages of scientific and reasonable dispatching decision-making, high efficiency and high intelligence.

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: The embodiments of the present disclosure relate to the field of communications, and in particular, to a cross-device link aggregation packet processing method and system, a switch and a storage medium. The method applied to a first switch in a cross-device link aggregation switch system includes: receiving a first packet sent by a gateway device; if the first address corresponding to the first packet is not found in the packet table entry, sending the first packet to the second switch through the first link, so that the second switch queries the first address according to the first packet, or acquires the first address from a server communicatively connection with the cross-device link aggregation switch system, and forwarding the first packet according to the first address; wherein the packet table entry stores a corresponding relationship between the first packet and the first address.

Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.

Abstract: Lightweight mechanisms provide a way to assert provenance when live streaming media content and establish provenance upon playback. For example, a provenance claim generator generates a key pair including a live-stream private key and live-stream public key. The claim generator signs, with a long-term private key reliably associated with a sender, manifest metadata including the live-stream public key, thereby producing a manifest signature. During live streaming, the claim generator signs respective portions of media content with the live-stream private key, producing portion signatures for the respective portions. A provenance claim validator receives the manifest signature and manifest metadata. The claim validator verifies the manifest metadata using a long-term public key (reliably associated with the sender) and the manifest signature.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.

Abstract: A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.