Patents by Inventor NING TAN

NING TAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210357800
    Abstract: Systems and methods are disclosed for distributed decentralized machine learning model training. In certain embodiments, a first node in a network may comprise a circuit configured to receive an initial machine learning model having an initial parameter set, apply the local data to update parameters of the initial machine learning model to generate an updated machine learning model, transmit a copy of the updated machine learning model from the first node to a plurality of neighboring nodes in the network via a network interface, receive, via the network interface, a modified machine learning model from a first neighboring node, the modified machine learning model having parameters set based on local data of the first neighboring node, modify the updated machine learning model based on the modified machine learning model, and apply the updated machine learning model to control operations at the first node.
    Type: Application
    Filed: May 13, 2020
    Publication date: November 18, 2021
    Inventors: Naman Sharma, Varun Reddy Boddu, Alphonsus John Kwok Kwong Heng, Hui Ning Tan
  • Publication number: 20210328577
    Abstract: Disclosed are an audio rate conversion system and an electronic apparatus. The audio rate conversion system includes an integrator-comb filter, a multi-rate filter and a first half-band filter, an input of the integrator-comb filter being accessed with digital audio data, an output of the integrator-comb filter being sequentially connected to the multi-rate filter and the first half-band filter; where, the integrator-comb filter is configured to reduce a rate of the digital audio data according to a preset decimation rate; the multi-rate filter is configured to convert a rate of digital audio data output by the integrator-comb filter into a rate of digital audio data corresponding to an accessed control signal according to the control signal; and the first half-band filter is configured to reduce a rate of digital audio data output by the multi-rate filter.
    Type: Application
    Filed: June 26, 2021
    Publication date: October 21, 2021
    Inventors: Liuan ZHANG, Jon Sweat DUSTER, Erkan ALPMAN, Yulin TAN, Ning ZHANG, Haigang FENG
  • Publication number: 20210313997
    Abstract: Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Erkan ALPMAN, Xiaofeng GUO, Jon Sweat DUSTER, Yulin TAN, Ning ZHANG, Haigang FENG
  • Publication number: 20210266004
    Abstract: A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 26, 2021
    Inventors: Xiaofeng GUO, Erkan ALPMAN, Jon Sweat DUSTER, Haigang FENG, Ning ZHANG, Yulin TAN
  • Publication number: 20210252579
    Abstract: A manufacturing method for a hot stamping component having an aluminium-silicon alloy coating, and a hot stamping component, said method comprising the following steps: a steel plate coated with an aluminium-silicon alloy coating is machined into a blank having a shape required for a part, and the blank is subjected to heat treatment and hot stamping. The blank heat treatment is two-stage or three-stage heating, and the temperature of the heating increases in steps. The steel plate coated with the aluminium-silicon alloy coating comprises a substrate, and the aluminium-silicon alloy coating on at least one surface of the substrate.
    Type: Application
    Filed: September 6, 2019
    Publication date: August 19, 2021
    Applicant: Baoshan Iron & Steel Co., Ltd.
    Inventors: Ning TAN, Jiang FU, Jiyao HONG, Xuehua FANG
  • Publication number: 20200270489
    Abstract: A butyl rubber reactive bonding layer for a pre-applied reactive-bonding waterproofing coiled material, a preparation method therefor, and a pre-applied reactive-bonding waterproofing coiled material, relating to the technical field of high-molecular pre-applied materials, are disclosed. The butyl rubber reactive bonding layer is prepared mainly from the following raw materials: 100 parts of a raw rubber, 9.5-15.5 parts of a linear tackifier containing a terminal hydroxyl structure and 12.5-19.5 parts of an active filler. The active filler includes active silicon dioxide and aluminium oxide.
    Type: Application
    Filed: December 28, 2017
    Publication date: August 27, 2020
    Applicant: BEIJING ORIENTAL YUHONG WATERPROOF TECHNOLOGY CO., LTD.
    Inventors: Yuqin XIONG, Ning YANG, Ning TAN, Yang LIU
  • Patent number: 10731266
    Abstract: The present disclosure provides a composite anode unit, comprising: a metal core rod; a metal layer coated on the metal core, wherein the metal layer is lead or lead alloy; a conductive ceramic layer coated on the metal layer, wherein the conductive ceramic layer comprises ?-PbO2—Al2O3 composite oxide; an active ceramic layer is coated on the conductive ceramic layer, wherein the active ceramic layer comprises ?-MnO2—Ti4O7 composite oxide. Methods for preparing the composite anode unit and an anode plate made from the composite anode unit are also provided.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: August 4, 2020
    Assignees: KUNMING HENDERA SCIENCE AND TECHNOLOGY CO., LTD., KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY, JINNING HENDERA SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Zhongcheng Guo, Hui Huang, Buming Chen, Xuelong Li, Panlong Zhu, Jin Dong, Mingxi Pan, Feng Huang, Taixiang Huang, Ning Tan, Chutao Huang
  • Patent number: 10683561
    Abstract: Method for directly producing a pickling-free hot-plated sheet strip product from molten steel comprising: obtaining a refined molten steel; thin strip continuous casting: a mixed gas of an inert gas and a reducing gas is used for protection in the billet casting process; hot rolling: the cast strip is levelled at a high temperature so as to improve the sheet shape and rolled to a suitable thickness so as to change the product specification, or provide a mechanical disruption action on the iron oxide skin on the surface of the cast strip; reduction annealing: a sectional reduction method is used to perform sectional reductions with the temperature held within two ranges, i.e., 450-600° C. and 700-1000° C., wherein the reduction is performed within a range of 450-600° C. for 1-5 minutes and within a range of 700-1000° C.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 16, 2020
    Assignee: Baoshan Iron & Steel Co., Ltd.
    Inventors: Jun Li, Ning Tan, Chuang Guan, Yuan Fang, Xinjian Ma
  • Publication number: 20190078224
    Abstract: The present disclosure provides a composite anode unit, comprising: a metal core rod; a metal layer coated on the metal core, wherein the metal layer is lead or lead alloy; a conductive ceramic layer coated on the metal layer, wherein the conductive ceramic layer comprises ?-PbO2—Al2O3 composite oxide; an active ceramic layer is coated on the conductive ceramic layer, wherein the active ceramic layer comprises ?-MnO2—Ti4O7 composite oxide. Methods for preparing the composite anode unit and an anode plate made from the composite anode unit are also provided.
    Type: Application
    Filed: December 18, 2017
    Publication date: March 14, 2019
    Inventors: Zhongcheng GUO, Hui HUANG, Buming CHEN, Xuelong LI, Panlong ZHU, Jin DONG, Mingxi PAN, Feng HUANG, Taixiang HUANG, Ning TAN, Chutao HUANG
  • Patent number: 10211303
    Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ning Tan, Weidong Tian
  • Patent number: 10209297
    Abstract: An apparatus with a burn-in board containing a microcontroller unit and a heater socket for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of multiple packaged integrated circuits while under stress.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: February 19, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Ning Tan, Jose Abdiel Rodriguez-Latorre
  • Publication number: 20170199238
    Abstract: An apparatus with a burn-in board containing a microcontroller unit and a heater socket for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of multiple packaged integrated circuits while under stress.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 13, 2017
    Inventors: Ning Tan, Jose Abdiel Rodriguez-Latorre
  • Publication number: 20170114427
    Abstract: Method for directly producing a pickling-free hot-plated sheet strip product from molten steel comprising: obtaining a refined molten steel; thin strip continuous casting: a mixed gas of an inert gas and a reducing gas is used for protection in the billet casting process; hot rolling: the cast strip is levelled at a high temperature so as to improve the sheet shape and rolled to a suitable thickness so as to change the product specification, or provide a mechanical disruption action on the iron oxide skin on the surface of the cast strip; reduction annealing: a sectional reduction method is used to perform sectional reductions with the temperature held within two ranges, i.e., 450-600° C. and 700-1000° C., wherein the reduction is performed within a range of 450-600° C. for 1-5 minutes and within a range of 700-1000° C.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 27, 2017
    Applicant: BAOSHAN IRON & STEEL CO.,LTD.
    Inventors: Jun Li, Ning Tan, Chuang Guan, Yuan Fang, Xinjian Ma
  • Publication number: 20170040332
    Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 9, 2017
    Inventors: Ning TAN, Weidong TIAN
  • Patent number: 9431253
    Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ning Tan, Weidong Tian
  • Patent number: 8681568
    Abstract: A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: March 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ning Tan
  • Publication number: 20140029348
    Abstract: A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.
    Type: Application
    Filed: September 30, 2013
    Publication date: January 30, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: NING TAN
  • Patent number: 8565025
    Abstract: A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: October 22, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ning Tan
  • Publication number: 20120268999
    Abstract: A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.
    Type: Application
    Filed: April 25, 2011
    Publication date: October 25, 2012
    Inventor: NING TAN