Abstract: The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents.

Abstract: Embodiments of the present disclosure provide a transport vehicle and an installation method for a case of a mobile power generation system. The transport vehicle includes: a chassis and a lifting mechanism assembly located on the chassis. The lifting mechanism assembly includes: a turning frame hinged to the chassis at a hinged position of the chassis, at least one turning hydraulic cylinder connected to the turning frame and the chassis, and a connecting frame configured to be detachably connected to the case. In the main beam, the first body portion is located between the hinged position and the second body portion, and a third plane in which a surface of the second body portion facing towards the turning frame is located is farther away from the connecting frame than the first plane.

Abstract: A tone mapping method is provided. This method includes: obtaining one or a plurality of high dynamic range images, and determining a storage format of each high dynamic range image; performing an image decomposition on the high dynamic range image to obtain a first component, a second component and a third component, when the storage format of the high dynamic range image is determined as a predetermined storage format; inputting the first component and the second component into a predetermined deep neural network, and using the deep neural network to perform mapping on the first component and the second component respectively to obtain a first mapped component and a second mapped component; and fusing the first mapped component and the second mapped component with the third component to obtain a fused low dynamic range image corresponding to the high dynamic range image.

Abstract: The present application provides an image processing method, an image processing device, a computer storage medium and a terminal, the image processing method includes: determining convolution kernels of at least two sizes for feature extraction; performing sparsity constraint for the determined convolution kernels of at least two sizes for feature extraction through a preset objective function; and performing feature extraction on an image based on the convolution kernels subjected to the sparsity constraint.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: Techniques are provided for applying plate tectonic model information to improve the accuracy of base station assisted satellite navigation systems. An example method for determining a location of a mobile device includes receiving base station measurement, coordinate and epoch information, receiving base station velocity information, receiving signals from a plurality of satellite vehicles, and determining the location of the mobile device based on the signals received from the plurality of satellite vehicles, the base station measurement, coordinate and epoch information, and the station velocity information.

Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.

Abstract: A connector assembly includes a connector, a circuit board having a first soldering pin and a second soldering pin electrically connected with the first soldering pin, a cable having a wire with a conductor, and an outer shield housing mounted on the circuit board and covering the connector, the cable, and the circuit board. The connector includes a shield housing, an insulation body disposed in the shield housing, and a conductive terminal held in the insulation body. The conductive terminal is soldered to the first soldering pin. The conductor is soldered to the second soldering pin.

Abstract: The present application relates to a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base plate, a plurality of pixel structures on the base plate, and a color resist layer on a side of the plurality of pixel structures away from the base plate. The color resist layer includes a plurality of color resist blocks, each color resist block corresponding to one or more of the plurality of pixel structures. Light emitted from each of the plurality of pixel structures has the same color as the color resist block corresponding thereto.

Abstract: A display substrate and a manufacturing method thereof, and a display device, are disclosed. The display substrate includes a base substrate and a thin film transistor (TFT) array, including a plurality of TFTs. A first electrode in each TFT includes a first portion and a second portion, a height of the second portion being greater than a height of the first portion in a direction perpendicular to the base substrate, wherein the first portion forms a groove with respect to the second portion and a wall of the groove comprises the second portion of the first electrode of a thin film transistor adjacent to the TFT. A bottom of the groove is the first pixel electrode of a light emitting element, wherein an organic light emitting functional layer is deposited in the groove on the first pixel electrode, and the second pixel electrode on the organic light emitting functional layer.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Abstract: This application provides a planar transformer and an active circuit, and may be applied to a telecommunications device and a communications power supply in fields such as a 5G mobile communications technology and cloud computing. The planar transformer includes a winding structure and a magnetic core structure. The winding structure includes a primary-side winding and a secondary-side winding. The magnetic core structure includes a first magnet part, a second magnet part, and a plurality of magnetic cylinders. The plurality of magnetic cylinders are located between the first magnet part and the second magnet part. The primary-side winding is wound around M magnetic cylinders in the plurality of magnetic cylinders, wherein M is a positive integer equal to or greater than three (3). A cross-sectional area of at least one of the M magnetic cylinders is different from a cross-sectional area of another magnetic cylinder.

Abstract: A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.

Abstract: According to one example, a semiconductor device includes a first region comprising a plurality of nanosheets vertically stacked above a substrate, a second region comprising a fin protruding from the substrate, a first gate structure wrapping around each of the nanosheets, and a second gate structure disposed over the top surface and sidewalls of the fin. A top surface of a topmost nanosheet of the plurality of nanosheets is vertically offset from a top surface of the fin.

Abstract: The present disclosure pertains to compositions comprising anti-VEGF proteins and methods for producing such compositions.

Abstract: A negative thermal expansion material and a preparation method thereof, and a negative thermal expansion film and a preparation method thereof are provided. The negative thermal expansion material includes Eu0.85Cu0.15MnO3-?, wherein 0???2.

Abstract: A display substrate includes a driving substrate and a stacked structure disposed at a side of the driving substrate. The stacked structure includes a plurality of emission layers and a plurality of carrier transport layers that are stacked in a direction perpendicular to the side of the driving substrate. The stacked structure forms a plurality of light-emitting devices, and each light-emitting device includes at least two emission portions that are respectively located in at least two emission layers. The plurality of light-emitting devices include a plurality of first light-emitting devices and a plurality of second light-emitting devices. Emission portions in each first light-emitting device are separated from each other. At least two emission portions in each second light-emitting device are adjacent to each other, and the at least two adjacent emission portions share at least one carrier transport layer.

Abstract: The present disclosure pertains to compositions comprising anti-VEGF proteins and methods for producing such compositions.

Abstract: The present disclosure pertains to compositions comprising anti-VEGF proteins and methods for producing such compositions.

Abstract: The present invention discloses a door for a refrigerator, a refrigerator and a method of manufacturing the door. The door comprises a door frame enclosed at a periphery, and a first side plate and a second side plate located on two opposed sides of the door frame, the door frame, the first side plate and the second side plate forming a receiving space for receiving a foaming material, wherein the door frame is provided with at least one material overflow preventing assembly which comprises an air discharge hole disposed on the door frame, a receiving cavity communicated with the air discharge hole, and a material discharging passage communicated with the receiving cavity, the air discharge hole is communicated with the external, and the material discharging passage is communicated with the receiving space. The present invention makes the manufacturing cost lower and the quality of products of the door higher.