Patents by Inventor Ning Ye

Ning Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240249950
    Abstract: Approaches directed at increasing the production yield of integrated circuits including layers of low-k dielectrics. One example provides a flip-chip assembly including a semiconductor chip attached to a substrate using pillars or bumps. The semiconductor chip has a thickness profile such that the chip is thinner near the corners than in middle portions. The thinner corner portions beneficially alleviate chip-integrity issues related to the stresses generated during the solder reflow operation while the thicker middle portions beneficially alleviate chip-integrity issues related to the stresses generated during the chip or die pick-up operation. Due to the alleviation of both types of chip-integrity issues, the number of instances in which the low-k dielectrics crack during the corresponding assembly operations is significantly reduced, thereby beneficially increasing the manufacturing yield.
    Type: Application
    Filed: August 14, 2023
    Publication date: July 25, 2024
    Inventors: Yangming Liu, Bo Yang, Ning Ye
  • Patent number: 12033958
    Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 9, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yangming Liu, Shenghua Huang, Bo Yang, Ning Ye, Cong Zhang
  • Patent number: 12016111
    Abstract: A protective enclosure for a PCB assembly, e.g., a solid-state-drive assembly. In an example embodiment, the enclosure comprises a flexible, stamped-metal heat spreader connected, by way of cured-liquid TIM parts, to at least some of the packaged integrated circuits on one side of the PCB assembly. In some embodiments, additional cured-liquid TIM parts may be connected between the body of the protective enclosure and packaged integrated circuits on the other side of the PCB assembly and/or the assembly's PCB. The PCB assembly, heat spreader, and various TIM parts are arranged in a manner that helps to significantly lower the risk of solder-joint failure under thermal cycling.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: June 18, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chun Sean Lau, Ahmad Faridzul Hilmi Shamsuddin, Bo Yang, Shankara Venkatraman Gopalan, Warren Middlekauff, Ning Ye
  • Patent number: 12013749
    Abstract: Methods and apparatus for detecting a failed temperature sensor within a data storage device and for mitigating the loss of the sensor are provided. One such data storage device includes a non-volatile memory (NVM), a set of temperature sensors, and a processor coupled to the NVM and the temperature sensors. The processor is configured to detect failure of one of the temperature sensors and obtain temperature data from the other temperature sensors. The processor is further configured to estimate, based on the obtained temperature data, the temperature at the failed sensor, and then control at least one function of the data storage device based on the estimated temperature, such as controlling entry into a Read Only mode. In some examples, the processor estimates the temperature at the failed sensor or at various virtual sensor locations using pre-determined formulas having offsets and coefficients determined during an initial machine learning calibration procedure.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: June 18, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hedan Zhang, Chaolun Zheng, Ning Ye, Bret Dee Winkler, Yanjun Xia, Wei Wu
  • Patent number: 11986958
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using skill templates for robotic demonstration learning. One of the methods includes receiving a skill template for a task to be performed by a robot, wherein the skill template defines a state machine having a plurality of subtasks and one or more respective transition conditions between one or more of the subtasks. Local demonstration data for a demonstration subtask of the skill template is received, where the local demonstration data is generated from a user demonstrating how to perform the demonstration subtask with the robot. A machine learning model is refined for the demonstration subtask and the skill template is executed on the robot, causing the robot to transition through the state machine defined by the skill template to perform the task.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 21, 2024
    Assignee: Intrinsic Innovation LLC
    Inventors: Bala Venkata Sai Ravi Krishna Kolluri, Stefan Schaal, Benjamin M. Davis, Ralf Oliver Michael Schönherr, Ning Ye
  • Publication number: 20240157554
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using simulated local demonstration data for robotic demonstration learning. One of the methods includes receiving perceptual data of a workcell of a robot to be configured to execute a task according to a skill template, wherein the skill template specifies one or more subtasks required to perform the skill, wherein at least one of the subtasks is a demonstration subtask that relies on learning visual characteristics of the workcell. A virtual model is generated of a portion of the workcell. A training system generates simulated local demonstration data from the virtual model of the portion of the workcell and tunes a base control policy for the demonstration subtask using the simulated local demonstration data generated from the virtual model of the portion of the workcell.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 16, 2024
    Inventors: Bala Venkata Sai Ravi Krishna Kolluri, Stefan Schaal, Ralf Oliver Michael Schönherr, Benjamin M. Davis, Ning Ye
  • Patent number: 11985782
    Abstract: A data storage device includes an enclosure and a Printed Circuit Board Assembly (PCBA) extending in a basal plane, and a plurality of semiconductor memory packages electromechanically bonded to the PCBA and coupled to the enclosure with thermal interface material. The data storage device further includes a first fitting coupled to a first end of the PCBA and the enclosure, restricting movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane. The data storage device further includes a second fitting coupled to a second end of the PCBA, allowing movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 14, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bo Yang, Warren Middlekauff, Sean Lau, Ning Ye, Shrikar Bhagath, Yangming Liu
  • Patent number: 11978713
    Abstract: The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: May 7, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
  • Patent number: 11961778
    Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 16, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
  • Publication number: 20240082073
    Abstract: Absorbent articles (30) have bonded materials and bond patterns. One of the absorbent articles (30) has a bond pattern (150a-150d) comprising bonds (151,153,155,155a-155d). The bond pattern (150a-150d) comprises a longitudinally extending series of bonds (151,153), which comprises a first bond (151) and a second bond (153) disposed longitudinally adjacent to the first bond (151). The first bond (151) has an inboard lateral edge (158), an outboard lateral edge (156), a top edge (152), and a bottom edge (154) having a recess portion (164). The second bond (153) has an inboard lateral edge (158) and an outboard lateral edge (156), a top edge (152) having a recess portion (164), and a bottom edge (154).
    Type: Application
    Filed: February 23, 2021
    Publication date: March 14, 2024
    Inventors: Jongmin Mun, Ning Ye, Xixi Miao, Qi Dai, Xiaomin Liu, Weizhi Guo, Jason Sieck
  • Publication number: 20240078258
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for jointly training an image embedding model and a text embedding model. In one aspect, a method comprises: processing data from a historical query log of a search system to generate a candidate set of training examples, wherein each training example comprises: (i) a search query comprising a sequence of one or more words, (ii) an image, and (iii) selection data characterizing how often users selected the image in response to the image being identified by a search result for the search query; selecting a plurality of training examples from the candidate set of training examples; and using the training data to jointly train the image embedding model and the text embedding model.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Zhen Li, Yi-ting Chen, Ning Ye, Yaxi Gao, Zijian Guo, Aleksei Timofeev, Futang Peng, Thomas J. Duerig
  • Publication number: 20240067627
    Abstract: The present invention relates to novel pyridazin-3-yl phenol compounds of formula (I): wherein R1, R2, R3, R4 and R5 are defined herein, which inhibit NOD-like receptor protein 3 (NLRP3) inflammasome activity. The invention further relates to the processes for their preparation, pharmaceutical compositions and medicaments containing them, and their use in the treatment of diseases and disorders mediated by NLRP3.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 29, 2024
    Inventors: Xiaobin Ge, Henri Mattes, Zhicong Shi, Mei Xia, Ning Ye
  • Patent number: 11908495
    Abstract: Disclosed herein is an electronic device that includes a pedestal that extends from a mounting surface of a base of the electronic device. The electronic device also includes a thermal interface material that is interposed between an interface surface of the pedestal and a data processing component, is in direct contact with the data processing component, and is in direct contact with a first portion and a second portion of the interface surface. The first portion of the interface surface of the pedestal has a first height, relative to the mounting surface of the base, and the second portion of the interface surface of the pedestal has a second height, relative to the mounting surface of the base and different than the first height.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: February 20, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Bo Yang, Yuhang Yang, Ning Ye
  • Patent number: 11898267
    Abstract: Crystalline NH4Be2BO3F2 or Be2BO3F (abbreviated as BBF) has nonlinear optical effect, is not deliquescent in the air, is chemically stable. They can be used in a variety of nonlinear optical fields and will pioneer the nonlinear optical applications in the deep UV band.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: February 13, 2024
    Assignee: FUJIAN INSTITUTE OF RESEARCH ON THE STRUCTURE OF MATTER, CHINESE ACADEMY OF SCIENCES
    Inventors: Ning Ye, Guang Peng, Min Luo, Ge Zhang, Yu Chen
  • Publication number: 20240004749
    Abstract: Methods and apparatus for detecting a failed temperature sensor within a data storage device and for mitigating the loss of the sensor are provided. One such data storage device includes a non-volatile memory (NVM), a set of temperature sensors, and a processor coupled to the NVM and the temperature sensors. The processor is configured to detect failure of one of the temperature sensors and obtain temperature data from the other temperature sensors. The processor is further configured to estimate, based on the obtained temperature data, the temperature at the failed sensor, and then control at least one function of the data storage device based on the estimated temperature, such as controlling entry into a Read Only mode. In some examples, the processor estimates the temperature at the failed sensor or at various virtual sensor locations using pre-determined formulas having offsets and coefficients determined during an initial machine learning calibration procedure.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Hedan Zhang, Chaolun Zheng, Ning Ye, Bret Dee Winkler, Yanjun Xia, Wei Wu
  • Publication number: 20230402361
    Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and reinforcing blocks on the substrate. The reinforcing blocks may be provided at positions on the substrate where mechanical stresses develop in the device during singulation, such as at curves and/or discontinuous points around the outline of the substrate, to add strength to the substrate.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shenghua Huang, Binbin Zheng, Shaopeng Dong, Songtao Lu, Rui Guo, Yangming Liu, Bo Yang, Ning Ye
  • Publication number: 20230395352
    Abstract: Apparatuses, systems, and methods for providing beams for controlling charges on a sample surface of charged particle beam system. In some embodiments, a module comprising a laser source configured to emit a beam. The beam may illuminate an area adjacent to a pixel on a wafer to indirectly heat the pixel to mitigate a cause of a direct photon-induced effect at the pixel. An electron beam tool configured to detect a defect in the pixel, wherein the defect is induced by the indirect heating of the pixel.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 7, 2023
    Applicant: ASML Netherlands B.V.
    Inventors: Ning YE, Jun JIANG, Jian ZHANG, Yixiang WANG
  • Publication number: 20230395446
    Abstract: A semiconductor device including one or more support structures for supporting a semiconductor-die stack having a region that overhangs a substrate. In an example embodiment, the support structures may be implemented using suitably shaped pieces of relatively thick round or ribbon wire attached to metal pads on the substrate. During the encapsulation operation, the one or more support structures may counteract a bending force applied to the semiconductor-die stack by a flow of the molding compound. At least some embodiments may beneficially be used, e.g., to enable high-yield fabrication of devices having sixteen or more stacked memory dies.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Yangming Liu, Shenghua Huang, Bo Yang, Ning Ye
  • Publication number: 20230385171
    Abstract: Methods, systems, and computer readable medium for personalizing an analytics user interface. The method includes generating a set of training data from received user interaction data, inputting the set of training data to a machine learning model to train the model, generating a set of user interest scores for the particular user that each indicate a user's interest in accessing information corresponding to a UI element of the application, determining, from the user interest scores, that the user is interested in a particular UI element that was not included in the initial UI and has at least a threshold score, dynamically modifying the initial UI to include the particular UI element, presenting the updated UI, monitoring further user interactions, updating the model based on the further user interactions, and modifying the updated UI based on the updated model.
    Type: Application
    Filed: April 21, 2023
    Publication date: November 30, 2023
    Inventors: Sundardas Samuel Dorai-Raj, Zilin Du, Nina Ning Ye, Ying Cheng, Wei Zhang, Annissa Al-Alusi
  • Publication number: 20230378112
    Abstract: The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shenghua HUANG, Yangming LIU, Bo YANG, Ning YE