Abstract: Backend processes in a storage system are implemented using a plurality of worker threads that are divided into two thread groups: thread group A and thread group B. Threads of thread group A are able to be used to process both Random Read Miss (RRM) workload items and Random Write Miss (RWM) workload items. Threads of thread group B are divided into two thread sub-groups: thread sub-group B1 and thread sub-group B2. Threads of thread sub-group B1 are able to be used to process both RRM and RWM workload items, while threads of thread sub-group B2 are reserved to be used to process only RRM workload items. The size of thread sub-group B2 relative to the size of thread sub-group B1 changes over time (from 0 threads to all threads of thread group B), depending on the duty cycle of the threads of group A.

Abstract: Emulation modules running on a single-board compute node have allocations of cores of a multi-core processor. The emulation modules are configured to donate underutilized cores or available CPU cycle units to a shared pool that can be used by other emulation modules running on the board. Emulation modules that require additional processing resources borrow cores or CPU cycle units from the shared pool. The emulation modules dynamically donate and retract cores or CPU cycle units from the shared pool based on utilization of allocated cores.

Abstract: Backend processes in a storage system are implemented using a plurality of worker threads that are divided into two thread groups: thread group A and thread group B. Threads of thread group A are able to be used to process both Random Read Miss (RRM) workload items and Random Write Miss (RWM) workload items. Threads of thread group B are divided into two thread sub-groups: thread sub-group B1 and thread sub-group B2. Threads of thread sub-group B1 are able to be used to process both RRM and RWM workload items, while threads of thread sub-group B2 are reserved to be used to process only RRM workload items. The size of thread sub-group B2 relative to the size of thread sub-group B1 changes over time (from 0 threads to all threads of thread group B), depending on the duty cycle of the threads of group A.

Abstract: Distributed failover of a failed BE, and failback of the failed BE when it recovers, are described. A separate pool of memory may be reserved for each BE on a storage system. Each such pool may be further divided into sub-pools. When a BE fails, the one or more other active BEs on the storage system may be notified, and each such active BE may attempt to take ownership of one or more sub-pools of the BE and execute the one or more pending write operations of the failed BE. Upon completing execution of the pending write operations in a failed-over sub-pool, the ownership of the sub-pool may be returned to the failed BE. When the failed BE recovers, the recovered BE may attempt to take back control of one or more of its sub-pools.

Abstract: Techniques for performing configuration may include: determining an initial distribution of logical devices among disk adapters, wherein the initial distribution assigns each logical device a designated disk adapter as a primary active disk adapter servicing I/Os directed to the logical device, wherein the logical devices have storage provisioned from a RAID group including physical storage devices, wherein the disk adapters concurrently issue I/Os to each of the physical storage devices; detecting a configuration change; and responsive to detecting a configuration change, performing first processing. The first processing may include determining, in accordance with the configuration change, a redistribution of the logical devices among the disk adapters; and draining pending I/Os. The configuration change may include adding or removing a logical device provisioned from the RAID group.

Abstract: Distributed failover of a failed BE, and failback of the failed BE when it recovers, are described. A separate pool of memory may be reserved for each BE on a storage system. Each such pool may be further divided into sub-pools. When a BE fails, the one or more other active BEs on the storage system may be notified, and each such active BE may attempt to take ownership of one or more sub-pools of the BE and execute the one or more pending write operations of the failed BE. Upon completing execution of the pending write operations in a failed-over sub-pool, the ownership of the sub-pool may be returned to the failed BE. When the failed BE recovers, the recovered BE may attempt to take back control of one or more of its sub-pools.

Abstract: Techniques for processing I/O operations may include performing DMA (direct memory access) operations between a data storage system, one or more physical storage devices, and a hardware component that communicate over at least one bus using a DMA-based protocol, such as NVMe (Non-Volatile Memory Express). The hardware device may perform encryption and decryption processing of data that is, respectively, stored to, and read from, physical non-volatile storage. The hardware device may optionally perform other processing for other data-related operations such as any of data validation and integrity checking, data deduplication, data compression, and data decompression. When performing DMA transfers, multiple descriptors, such as SGLs (scatter gather lists) or PRPs (physical region pages), for multiple data portions having logically contiguous consecutive logical addresses may be combined into a single descriptor sent in a single DMA operation.

Abstract: Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache area in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes loading data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, where the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different processors may be placed on different directors.

Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.

Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.

Abstract: Techniques for processing I/O operations may include performing DMA (direct memory access) operations between a data storage system, one or more physical storage devices, and a hardware component that communicate over at least one bus using a DMA-based protocol, such as NVMe (Non-Volatile Memory Express). The hardware device may perform encryption and decryption processing of data that is, respectively, stored to, and read from, physical non-volatile storage. The hardware device may optionally perform other processing for other data-related operations such as any of data validation and integrity checking, data deduplication, data compression, and data decompression. When performing DMA transfers, multiple descriptors, such as SGLs (scatter gather lists) or PRPs (physical region pages), for multiple data portions having logically contiguous consecutive logical addresses may be combined into a single descriptor sent in a single DMA operation.

Abstract: Techniques for performing configuration may include: determining an initial distribution of logical devices among disk adapters, wherein the initial distribution assigns each logical device a designated disk adapter as a primary active disk adapter servicing I/Os directed to the logical device, wherein the logical devices have storage provisioned from a RAID group including physical storage devices, wherein the disk adapters concurrently issue I/Os to each of the physical storage devices; detecting a configuration change; and responsive to detecting a configuration change, performing first processing. The first processing may include determining, in accordance with the configuration change, a redistribution of the logical devices among the disk adapters; and draining pending I/Os. The configuration change may include adding or removing a logical device provisioned from the RAID group.

Abstract: Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache area in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes loading data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, where the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different processors may be placed on different directors.

Abstract: Described are techniques for processing data operations. A read request for first data is received at a data storage system. It is determined whether the read request results in a cache hit whereby the first data is stored in a cache of the data storage system, or whether the read request otherwise results in a cache miss. If the read request results in a cache miss, processing is performed to determine determining whether to perform cacheless read processing or deferred caching processing to service the read request. Determining whether to perform cacheless read processing or deferred caching processing is performed in accordance with criteria including a measurement indicating a level of busyness of a back-end component used to retrieve from physical storage any portion of the first data not currently stored in the cache.