Abstract: New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: The independent claims of this patent signify a concise description of embodiments. New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: The independent claims of this patent signify a concise description of embodiments. New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.

Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.

Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.

Abstract: Magnetoresistive (MR) sensors are disclosed having mechanisms for reducing edge effects such as Barkhausen noise. The sensors include a pinned layer and a free layer with an exchange coupling layer adjoining the free layer, and a ferromagnetic layer having a fixed magnetic moment adjoining the exchange coupling layer. The exchange coupling layer and ferromagnetic layer form a synthetic antiferromagnetic structure with part of the free layer, providing bias that reduces magnetic instabilities at edges of the free layer. Such synthetic antiferromagnetic structures can provide a stronger bias than conventional antiferromagnetic layers, as well as a more exactly defined track width than conventional hard magnetic bias layers. The synthetic antiferromagnetic structures can also provide protection for the free layer during processing, in contrast with the trimming of conventional antiferromagnetic layers that exposes if not removes part of the free layer.

Abstract: A method and system for providing a magnetoresistive sensor is disclosed. The method and system include providing a first pinned layer, providing a free layer having a length, and providing a first spacer layer disposed between the first pinned layer and the free layer. The first spacer layer has a first interface with the first pinned layer. The method and system also include providing a second pinned layer and providing a second spacer layer disposed between the free layer and the second pinned layer. The second spacer layer has a second interface with the second pinned layer. A direction of a current passed through the magnetoresistive sensor is through the first interface, through the second interface, and along at least a portion of the length of the free layer.

Abstract: A method and system for providing a magnetoresistive head that reads data from a recording media is disclosed. The method and system include providing a first shield, a second shield, a magnetoresistive sensor, and a lead. The first shield has a first end, a central portion and a second end. The first end is closer to the recording media during use than the second end. The second shield has a first end, a central portion, and a second end. The first end of the second shield is separated from the first end of the first shield by a read gap. The central portion of the second shield is separated from the central portion of the first shield by a distance that is greater than the read gap. The magnetoresistive sensor is disposed between the first shield and the second shield and has a front end and a back end. The front end of the magnetoresistive sensor is electrically coupled with the first end of the first shield or the first end of the second shield.

Abstract: A method and system for providing a spin valve for use in a magnetoresistive head is disclosed. The method and system include providing a synthetic pinned layer, a nonmagnetic spacer layer, and a free layer. The free layer has a first magnetization canted from a first direction by a first angle. The nonmagnetic spacer layer is disposed between the free layer and the synthetic pinned layer. The synthetic pinned layer has a second magnetization in a second direction. The second direction is canted from a third direction that is transverse to the first direction by a second angle. The second magnetization is substantially orthogonal to the first magnetization.

Abstract: A method and system for providing a spin valve for use in a magnetoresistive head is disclosed. The method and system include providing a synthetic pinned layer, a nonmagnetic spacer layer, and a free layer. The free layer has a first magnetization canted from a first direction by a first angle. The nonmagnetic spacer layer is disposed between the free layer and the synthetic pinned layer. The synthetic pinned layer has a second magnetization in a second direction. The second direction is canted from a third direction that is transverse to the first direction by a second angle. The second magnetization is substantially orthogonal to the first magnetization.

Abstract: A hybrid dual spin valve sensor includes a standard spin valve sharing a common free layer with a synthetic spin valve. The standard spin valve consists of a first antiferromagnetic layer having a first blocking temperature, a first soft ferromagnetic layer, a first spacer layer, and the common free layer. The synthetic spin valve consists of the common free layer, a second spacer, a second soft ferromagnetic layer, a third spacer layer, a third soft ferromagnetic layer, and a second antiferromagnetic layer having a second blocking temperature. Each of the two antiferromagnetic layers has a fixed magnetization orientation antiparallel to the other. A lead set configured to pass a sensing current from a current source through the hybrid dual spin valve, and a sensing circuit configured to measure changes in resistance within the hybrid dual spin valve, complete the sensor.

Abstract: A system and method for providing a spin valve is disclosed. The spin valve is formed on a substrate. In one aspect, the method and system include providing a seed layer including NiFe above the substrate and providing an antiferromagnetic layer on the seed layer. The seed layer provides the desired texture for the antiferromagnetic layer. The seed layer could include NiFeCr, NiFeNb, NiFeRh, or a NiFe/Cu multilayer. The method and system further include providing a pinned layer above the antiferromagnetic layer, the pinned layer being exchange coupled to the antiferromagnetic layer, providing a spacer layer above the pinned layer and providing a free layer above the spacer layer. In a second aspect, the method and system include providing a seed layer including Cu instead of NiFe. In a third aspect, the method and system include providing a synthetic antiferromagnetic layer in lieu of the antiferromagnetic layer and the pinned layer.