Patents by Inventor Nippon Raval
Nippon Raval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860797Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.Type: GrantFiled: December 30, 2021Date of Patent: January 2, 2024Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Nippon Raval, David A. Kaplan, Donald P. Matthews, Jr.
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Publication number: 20230315625Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventors: NIPPON RAVAL, PHILIP NG, ROSTISLAV S. DOBRIN
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Patent number: 11726693Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.Type: GrantFiled: December 29, 2020Date of Patent: August 15, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Nippon Raval
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Publication number: 20230229603Abstract: Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.Type: ApplicationFiled: December 30, 2021Publication date: July 20, 2023Inventors: PHILIP NG, NIPPON RAVAL, DAVID A. KAPLAN, DONALD P. MATTHEWS, JR.
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Patent number: 11698860Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.Type: GrantFiled: December 28, 2020Date of Patent: July 11, 2023Assignee: ATI TECHNOLOGIES ULCInventors: Nippon Raval, Philip Ng, Rostislav S. Dobrin
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Publication number: 20230214346Abstract: Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: NIPPON RAVAL, PHILIP NG, JAROSLAW MARCZEWSKI
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Patent number: 11567666Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.Type: GrantFiled: March 24, 2021Date of Patent: January 31, 2023Assignee: ATI Technologies ULCInventors: Philip Ng, Nippon Raval
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Patent number: 11550722Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.Type: GrantFiled: March 2, 2021Date of Patent: January 10, 2023Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
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Publication number: 20220308755Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Inventors: Philip Ng, Nippon Raval
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Publication number: 20220308756Abstract: An electronic device includes an input-output memory management unit (IOMMU). The IOMMU receives, from an input-output device, a memory access request directed to a given page of memory. The IOMMU then determines a particular encryption key from among a plurality of encryption keys associated with an owning entity to which the given page of memory is assigned. The IOMMU next communicates, to a encryption functional block, a specification of the particular encryption key to be used for encryption-related operations for processing the memory access request.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: Nippon Raval, Philip Ng
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Publication number: 20220283946Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.Type: ApplicationFiled: March 2, 2021Publication date: September 8, 2022Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
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Publication number: 20220206942Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: NIPPON RAVAL, PHILIP NG, ROSTISLAV S. DOBRIN
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Publication number: 20220206700Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Philip Ng, Nippon Raval
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Patent number: 10509736Abstract: An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.Type: GrantFiled: April 10, 2018Date of Patent: December 17, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Nippon Raval, David A. Kaplan, Philip Ng
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Publication number: 20180232320Abstract: An input-output (IO) memory management unit (IOMMU) uses a reverse map table (RMT) to ensure that address translations acquired from a nested page table are correct and that IO devices are permitted to access pages in a memory when performing memory accesses in a computing device. A translation lookaside buffer (TLB) flushing mechanism is used to invalidate address translation information in TLBs that are affected by changes in the RMT. A modified Address Translation Caching (ATC) mechanism may be used, in which only partial address translation information is provided to IO devices so that the RMT is checked when performing memory accesses for the IO devices using the cached address translation information.Type: ApplicationFiled: April 10, 2018Publication date: August 16, 2018Inventors: Nippon Raval, David A. Kaplan, Philip Ng