Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

Abstract: A control system, that includes a primary controller and various auxiliary controllers, is configured to facilitate a built-in self-test (BIST) of a system-on-chip (SoC). The primary controller is configured to initiate a BIST sequence associated with the SoC. Based on the BIST sequence initiation, each auxiliary controller is configured to schedule execution of various self-test operations on various functional circuits, various memories, and various logic circuits of the SoC by various functional BIST controllers, various memory BIST controllers, and various logic BIST controllers of the SoC, respectively. Based on the execution of the self-test operations, each auxiliary controller further generates various status bits with each status bit indicating whether at least one functional circuit, at least one memory, or at least one logic circuit is faulty. Based on the status bits generated by each auxiliary controller, a fault diagnosis of the SoC is initiated.

Abstract: An error management system can include register sets associated with an error reaction. The test errors are injected in functional signals based on activation of multiple bits in one of the register sets. When the functional signals with the injected test errors are received by the error management system, multiple bits in the other register set are activated. The error management system generates an activated indication signal when a number of the activated bits in one register set matches a number of activated bits in the other register set. When the indication signal is activated, the error management system generates a reaction signal indicative of the error reaction. Thus, the error management system generates a single reaction signal in response to the injected test errors requiring the same reaction.

Abstract: Embodiments of the present invention provide a system for automatically identifying and mapping interaction attributes to generate custom assessment functionality. The system is configured for identifying one or more interaction channels associated with an entity, gathering flow sets associated with the one or more interaction channels, identifying one or more segments associated with the one or more interaction channels based on the flow sets, mapping one or more attributes with the one or more segments, and generating an assessment functionality based on mapping the one or more attributes with the one or more segments.

Abstract: Aspects of the disclosure relate to computing systems for receiving user requests through channels of a webpage and performing computational functions corresponding to the user requests. In one embodiment, a computing platform may detect a change corresponding to input parameters for performing a user request through a first representation of a webpage. The computing platform may update, based on the detected change corresponding to the input parameters, a natural language processing application associated with a second representation of the webpage. The computing platform may generate, based on the updated natural language processing application associated with the second representation of the webpage, a logical table including one or more questions to ask a user through the second representation of the webpage in response to one or more user inputs.

Abstract: Aspects of the disclosure relate to computing systems for receiving user requests through channels of a webpage and performing computational functions corresponding to the user requests. In one embodiment, a computing platform may detect a change corresponding to input parameters for performing a user request through a first representation of a webpage. The computing platform may update, based on the detected change corresponding to the input parameters, a natural language processing application associated with a second representation of the webpage. The computing platform may generate, based on the updated natural language processing application associated with the second representation of the webpage, a logical table including one or more questions to ask a user through the second representation of the webpage in response to one or more user inputs.

Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

Abstract: An integrated circuit (IC) that is operable in scan test and functional modes includes scan-in pads, scan-out pads, scan chains, a compressor, a decompressor, a test control register, and a scan controller. The scan controller includes a multiple input shift register (MISR), an inverter, and multiple logic gates. The scan-in and scan-out pads receive scan test data and masking signals, respectively. The decompressor provides decompressed scan test data to the scan chains, which generate functional responses based on the decompressed scan test data. The compressor provides compressed functional responses to the scan controller. The logic gates receive the compressed functional responses and the masking signals from the compressor and the corresponding scan-out pads, respectively, and generate corresponding masked signals. The masking signals mask non-deterministic values in the decompressed functional responses. The MISR receives the masked signals and generates an error free signature.

Abstract: A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.

Abstract: A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.

Abstract: A system and method for determining power leakage of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool that includes a processor and an automatic test pattern generation (ATPG) tool for generating multiple sets of input value strings. The ATPG tool generates test patterns that include input value strings for simulating each digital logic element of the circuit design independently. A mapping between generated output values and corresponding input values is stored in a look up table (LUT). Thereafter, the ATPG tool generates test patterns that include input value strings for simulating the real-time behavior of the circuit design. The processor determines power leakage of the circuit design based on probability of occurrence of each unique input value string at the input of each digital logic element and corresponding predetermined power leakage values.

Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.

Abstract: Scan chains are used to detect faults in integrated circuits but with the size of today's circuits, it is difficult to detect and locate scan chain faults, especially when the scan data in and scan data out have been compressed. A method for debugging scan chains includes selecting a scan chain for debugging using a scan chain selection block and then providing scan test vectors to the selected scan chain. The scan test vectors undergo various scan test stages to generate scan response vectors. The scan response vectors are compared with ideal response vectors to identify a failing scan chain.