Patents by Inventor Nipun Padha

Nipun Padha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase locked loop (PLL) for integrated circuits
    Patent number: 6888385
    Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree. “This enables the PLL to maintain the proper phase even during a sleep mode of operation.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 3, 2005
    Assignee: STMicroelectronics PVT. Ltd.
    Inventors: Rajesh Bajaj, Nipun Padha
  • Phase locked loop (PLL) for integrated circuits
    Publication number: 20040104750
    Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree.
    Type: Application
    Filed: August 12, 2003
    Publication date: June 3, 2004
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Rajesh Bajaj, Nipun Padha