Patents by Inventor NIR ATZMON
NIR ATZMON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9990305Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.Type: GrantFiled: September 19, 2014Date of Patent: June 5, 2018Assignee: NXP USA, Inc.Inventors: Nir Baruch, Nir Atzmon, David W. Todd
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Patent number: 9619405Abstract: A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. The protection unit contains protection data defining access rights of source units to access specified address ranges of the target memory, and a system bus interface interfacing to a source unit and a memory bus interface interfacing to the target memory via a controller. The protection unit has a control monitor for detecting an indirect memory access request, and an indirect address monitor for comparing requested address data to specified address ranges and subsequently grant the indirect memory access in accordance with access rights of the respective source unit.Type: GrantFiled: November 24, 2014Date of Patent: April 11, 2017Assignee: NXP USA, INC.Inventors: Nir Atzmon, Eran Glickman, Tal Siton
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Patent number: 9529745Abstract: A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.Type: GrantFiled: February 26, 2014Date of Patent: December 27, 2016Assignee: NXP USA, INC.Inventors: Nir Atzmon, Ron-Michael Bar, Eran Glickman, Benny Michalovich
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Patent number: 9400654Abstract: A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state.Type: GrantFiled: June 27, 2014Date of Patent: July 26, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Nir Atzmon, Ron-Michael Bar, Eran Glickman, Stas Yosupov
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Publication number: 20160147672Abstract: A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. The protection unit contains protection data defining access rights of source units to access specified address ranges of the target memory, and a system bus interface interfacing to a source unit and a memory bus interface interfacing to the target memory via a controller. The protection unit has a control monitor for detecting an indirect memory access request, and an indirect address monitor for comparing requested address data to specified address ranges and subsequently grant the indirect memory access in accordance with access rights of the respective source unit.Type: ApplicationFiled: November 24, 2014Publication date: May 26, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: NIR ATZMON, ERAN GLICKMAN, TAL SITON
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Patent number: 9330024Abstract: A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.Type: GrantFiled: October 9, 2014Date of Patent: May 3, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Eran Glickman, Nir Atzmon, Ron-Michael Bar, Benny Michalovich
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Publication number: 20160103769Abstract: A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.Type: ApplicationFiled: October 9, 2014Publication date: April 14, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ERAN GLICKMAN, NIR ATZMON, RON-MICHAEL BAR, BENNY MICHALOVICH
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Publication number: 20160085687Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: NIR BARUCH, NIR ATZMON, DAVID W. TODD
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Publication number: 20150379276Abstract: A system on a chip for securing data is described. The system on a chip comprises: a controller arranged to: partition a data block into a plurality of segments; and determine and extract a subset of the plurality of segments to be compressed. A compressor logic circuit is arranged to receive and compress the subset of the plurality of segments. The controller is arranged to retrieve the compressed subset of the plurality of segments from the compressor logic circuit and attach the compressed subset of the plurality of segments to a remainder of the partitioned data block for transmission.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ERAN GLICKMAN, NIR ATZMON, RON-MICHAELO BAR
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Publication number: 20150378730Abstract: A system on a chip comprises a managing processor for controlling operations of the system on a chip. The managing processor comprises a core monitor control logic circuit operable to: receive at least one instruction; determine whether the instruction is an activation instruction; determine whether the managing processor is in or transitioning to an idle state; and transition the managing processor from a first mode of operation to a second mode of operation in response to the instruction being an activation instruction and the managing processor being in or transitioning to an idle state.Type: ApplicationFiled: June 27, 2014Publication date: December 31, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: NIR ATZMON, RON-MICHAEL BAR, ERAN GLICKMAN, STAS YOSUPOV
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Publication number: 20150242343Abstract: A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: NIR ATZMON, RON-MICHAEL BAR, ERAN GLICKMAN, BENNY MICHALOVICH