Patents by Inventor Nir Segev

Nir Segev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Routing instructions in a microprocessor
    Patent number: 12210908
    Abstract: A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 28, 2025
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Thompto, Michael Joseph Genden, Tharunachalam Pindicura, Phillip G. Williams, Kent Li, Nir Segev, Mehul Patel
  • ROUTING INSTRUCTIONS IN A MICROPROCESSOR
    Publication number: 20220413911
    Abstract: A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Brian W. Thompto, Michael Joseph Genden, Tharunachalam Pindicura, Phillip G. Williams, Kent Li, Nir Segev, Mehul Patel