Abstract: Systems, computer program products, and methods are described for dynamic power management in signal conductors, such as PCIe links. An example system determines an imminent change in link usage based on a combination of the received historical and predicted link usage information. In response, the example system either triggers a transition from a current operational state to a subsequent operational state, or dynamically adjusts a time period associated with the transition of the signal conductor from a current operational state to a subsequent operational state. These operational states are defined within a predefined sequence of operational power states, ranging from low-power states to active states. The adjustment of the transition time period serves as a mechanism to accommodate variations in link usage patterns, ensuring that transitions between operational states are both timely and efficient, optimizing the link's operational efficiency and reducing potential delays in data processing.

Abstract: An interconnect device is provided. In one example, an interconnect device includes circuits capable of receiving a request via an ingress port; in response to receiving the request, identifying one or more egress ports associated with the ingress port; activating the one or more egress ports associated with the ingress port; receiving data via the ingress port; processing the received data to identify an egress port associated with a destination of the data; and scheduling the data to be forwarded from the egress port associated with the destination of the data.

Abstract: An interconnect device is provided. In one example, an interconnect device includes ports and circuits to receive measurements from two or more switching devices; determine, based on the measurements, a relative power consumption of each switching device from the two or more switching devices; generate, based on the relative power consumption of each switching device from the two or more switching devices, respective power instructions for each switching device from the two or more switching devices; and distribute the respective power instructions to each switching device from the two or more switching devices.

Abstract: An interconnect device is provided. In one example, an interconnect device includes ports and a power profile controller to receive a power profile, monitor one or more of data traversing the switch and power consumption of the switch, and during a first time period determine at least one of an ingress bandwidth exceeds a first bandwidth threshold and the power consumption exceeds a first power threshold. At least one of the first bandwidth threshold and the first power threshold is defined in the power profile. During the first time period, the power profile controller is to, in response to determining the at least one of the ingress bandwidth exceeds the first bandwidth threshold and the power consumption exceeds the first power threshold, limit one or more of the data traversing the switch and the power consumption of the interconnect device.

Abstract: Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.

Abstract: Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.

Abstract: Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.

Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.

Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.

Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.

Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.