Abstract: A novel and useful self-calibration based production line testing mechanism utilizing built-in closed loop measurements in the radio to calibrate the output power of an external power amplifier coupled to a SoC radio. The mechanism is applicable during production line testing and calibration which is performed on each SoC and associated external power amplifier after assembly at the target PCB of the final product. The mechanism calibrates the TX output power in three phases based on loopback EVM measurements. In a first phase, the PPA in the radio (SoC) is calibrated and gain versus output power is stored in a gain table in on-chip NVS. In a second phase, the maximum PPA TX power is determined using closed loop EVM measurements. The external PA is calibrated in a third phase and the maximum PA power is determined. During this third phase, the maximum power of the device is calculated, compared to the requirements of the particular standard and a pass/fail determination is thereby made.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q) fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. A synthesizer provides 4/3 the desired frequency fRF. This frequency is divided by two to obtain in-phase and quadrature square waves at ? fRF. The in-phase signal is divided by two again to obtain in-phase and quadrature square waves at ? fRF. The signals are then logically combined using XOR operations to obtain I and Q branch signals containing spectral spurs. Since the spurs are located in non-disturbing bands, they can be filtered out resulting in the desired output signal.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The use of analog mixers of the prior art is avoided and replaced with an XOR gate configured to generate the correct average frequency. The edges are dynamically adjusted by ±T/12 or zero based on the state of the controlled oscillator down-divided clock.

Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.

Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/ƒT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.

Abstract: A novel and useful apparatus for and method of packet detection and carrier frequency offset estimation. The packet detection mechanism is robust to channels and sustains reasonable miss-detect (and false alarm) rates at low SNR values. The mechanism uses a modified combined cross correlation and delay and correlate scheme. A delay and correlate scheme is used in order to handle the effects of multipath while swapping integration and multiplication to increase cross-correlation factors resulting in improved sensitivity in low SNR conditions. Correlation is divided into multiple chains to generate a plurality of partial correlations to observe short patterns in the spread sequence resulting in improved performance in long multipath channels.

Abstract: System and method for enabling the coexistence of multiple wireless communications on a single unit. A preferred embodiment comprises receiving a schedule of reserved message transfer times from a coexistence unit of a first wireless network in a mobile unit at a coexistence unit of a second wireless network in the mobile unit, selecting an operating mode for the coexistence unit based on the schedule, and transferring messages on the first wireless network and the second wireless network based on the schedule. The first wireless network is restricted to being able to transfer messages only during scheduled times. The sharing of the schedule of reserved message transfer times can enable the transfer of messages in the second wireless network to occur in between the reserved message transfer times, thereby reducing message collisions that can negatively impact data transfer performance of both wireless networks.

Abstract: A novel system and method for correcting the residual phase offset between a recovered pilot signal and the received stereo signal. The invention uses a Costas loop as an auxiliary loop in addition to the pilot recovery phase locked loop (PLL) to lock onto the stereo component itself. This auxiliary loop functions to generate a pilot to stereo component phase correction signal that is added to the stereo carrier phase The resultant phase is used to generate the recovered pilot carrier used to demodulate the stereo MPX signal. The Costas loop is activated together with the main pilot recovery PLL that locks onto the pilot tone in the demodulated MPX signal. The auxiliary Costas loop is operative to track and determine a residual phase error of up to several degrees.

Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.

Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Abstract: The proposed Multiple Input Multiple Output (MIMO) transmitter/receiver system having a reduced complexity decoder for receiving and decoding simultaneously a plurality of transmitted signals, wherein said transmitter includes a space time coded modulation (STCM) block. The transmitter/receiver system provides a reduced complexity approximation of optimal MLE methods while maintaining most of the performance gain and simplifying the implementation All the above make the proposed transmitter/receiver worthwhile and much more efficient than existing methodologies.

Abstract: A method for processing an input signal having an input peak-to-average (PAR) so as to generate an output signal having an output PAR and a permitted spectral mask. The method includes generating a difference signal proportional to an amount by which the input signal exceeds a predetermined threshold, and filtering the difference signal with a filter having a spectral response that is determined responsively to the permitted spectral mask. The filtered difference signal is subtracted from the input signal to generate the output signal so that the output PAR is adjusted relative to the input PAR. Typically, the output PAR is reduced relative to the input PAR.

Abstract: The present invention discloses a novel scheme of performing frequency domain filtering that does not require a Hilbert transform and which is faster than equivalent FIR filtering schemes. Such a scheme has applications in implementing filters in voice band modems on OSP platforms and in numerous other applications as well. The scheme of the present invention is shown to be superior in term of CPU resource consumption and memory storage space when compared with an equivalent implementation using prior art time domain convolution techniques. The scheme of the present invention permits the delay buffer in the far end echo canceler to store the signal in real format rather than complex format, thus reducing memory requirements by half. The present invention implements a real to analytic fast convolution in the frequency domain which uses zero CPU resources.

Abstract: The present invention discloses a novel scheme of performing frequency domain filtering that does not require a Hilbert transform and which is faster than equivalent FIR filtering schemes. Such a scheme has applications in implementing filters in voice band modems on OSP platforms and in numerous other applications as well. The scheme of the present invention is shown to be superior in term of CPU resource consumption and memory storage space when compared with an equivalent implementation using prior art time domain convolution techniques. The scheme of the present invention permits the delay buffer in the far end echo canceler to store the signal in real format rather than complex format, thus reducing memory requirements by half. The present invention implements a real to analytic fast convolution in the frequency domain which uses zero CPU resources.

Abstract: An apparatus for and method of implementing a novel buffer based full duplex communication system is disclosed. The disclosed invention is particularly useful in native signal processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, echo canceler, CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel buffer switching mechanism to optimize the tradeoff between processing response time, on one hand, and robustness to interrupt latency and processor implementation on the other hand.

Abstract: A novel system by which the utilization of a central processing unit (CPU) in performing filtering operations can be reduced by shortening the filter's length thus degrading the performance of the system down to a predetermined level or threshold. The present invention is applicable to such systems that incorporate filters whereby shortening their length decreases the performance of the system and to such systems where a reliable quality criteria exists that can be measured during run time. A method iteratively minimizes the filter's length so that the quality criteria does not fall below a predetemined threshold level. In addition, a signal to noise ratio (SN) criteria is suggested for estimating the quality of the reception of communication signals. An implementation is suggested for the method in the particular case of an echo cancellation adaptive filter. In addition, a method for determining an immediate approximation of the echo canceler filter's length as opposed to finding it iteratively.

Abstract: An apparatus for and method of implementing a novel buffer based fall duplex communication system is disclosed. The disclosed invention is particularly useful in native signal processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel dynamic buffer size mechanism to optimize the tradeoff between buffer delay and processing time period, on one hand, and robustness to interrupt latency and processor availability on the other hand. Small buffers provide the communication system with short, accurate response times in addition to short processing times.

Abstract: An apparatus for and method of implementing a novel buffer ba full duplex communication system is disclosed. The disclosed invention is particularly useful in native sign processing systems wherein heavy contention of processor resources typically exist, such as in systems running multi-tasking operating systems. The communication system of the present invention includes a receiver, transmitter, echo canceler. CODEC and telephone hybrid. The major components of the system operate on a buffer of input samples consisting of a set of input bits. The communication system operates to generate a buffer of output samples consisting of a set of output bits. The invention utilizes a novel buffer switching mechanism to optimize the tradeoff between processing response time, on one hand, and robustness to interrupt latency and processor implementation on the other hand.