Patents by Inventor Nir Tasher
Nir Tasher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907559Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Itay Admon, Uri Kaluzhny, Nir Tasher
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Publication number: 20240053913Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.Type: ApplicationFiled: August 9, 2022Publication date: February 15, 2024Inventors: Itay Admon, Uri Kaluzhny, Nir Tasher
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Patent number: 10915329Abstract: A memory device includes a non-volatile memory (NVM) and circuitry. The circuitry is configured to initialize and prepare the NVM for executing memory-access operations for a processor, and to ascertain that no memory-access operations are received from the processor before the NVM is ready, by preventing the processor from bootstrapping during at least part of initialization and preparation of the NVM.Type: GrantFiled: February 24, 2019Date of Patent: February 9, 2021Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Itay Admon, Nir Tasher, Mark Luko
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Publication number: 20200272480Abstract: A memory device includes a non-volatile memory (NVM) and circuitry. The circuitry is configured to initialize and prepare the NVM for executing memory-access operations for a processor, and to ascertain that no memory-access operations are received from the processor before the NVM is ready, by preventing the processor from bootstrapping during at least part of initialization and preparation of the NVM.Type: ApplicationFiled: February 24, 2019Publication date: August 27, 2020Inventors: Itay Admon, Nir Tasher, Mark Luko
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Patent number: 10754988Abstract: A secured storage system includes a non-volatile memory and a controller. The non-volatile memory is configured to store a first data item and a respective first version identifier assigned to the first data item. The controller is configured to receive a second data item accompanied by a second version identifier and a signature, for replacing the first data item in the non-volatile memory, to authenticate at least the second version identifier using the signature, to make a comparison between the stored first version identifier and the second version identifier, and to replace the first data item with the second data item only in response to verifying that (i) the second version identifier is authenticated successfully, and (ii) the second data item is more recent than the first data item, as indicated by the comparison between the stored first version identifier and the authenticated second version identifier.Type: GrantFiled: August 7, 2017Date of Patent: August 25, 2020Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Itay Admon
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Patent number: 10757087Abstract: A memory subsystem includes a memory interface for accessing a non-volatile memory (NVM), a host interface for communicating with a host, and a processor. The processor is configured to calculate a signature over program code that is used by the host and is stored in the NVM, to verify, upon detecting a boot process performed by the host, whether the boot process is legitimate, and, only if the boot process was verified to be legitimate, to provide the signature to the host for authentication to a remote server.Type: GrantFiled: January 2, 2018Date of Patent: August 25, 2020Assignee: WINBOND ELECTRONICS CORPORATIONInventor: Nir Tasher
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Patent number: 10482036Abstract: A memory system includes an interface, a non-volatile memory and a controller. The interface is configured to communicate over an unsecured communication link with an external host. The non-volatile memory is pre-programmed with a device identifier and a corresponding initialization key that are additionally stored in a database that resides externally to the memory system, and is securely accessible by the host. The controller is configured to send the device identifier to the host, to receive from the host, via the interface, binding information that was generated in the host, to generate, using at least the received binding information and the pre-programmed initialization key, a first binding key that matches a second binding key that is generated in the host based on an initialization key securely obtained by the host from the database, and to securely communicate with the host over the communication link using the first binding key.Type: GrantFiled: August 31, 2017Date of Patent: November 19, 2019Assignee: Winbond Electronics CorporationInventors: Itay Admon, Nir Tasher
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Patent number: 10374791Abstract: An electronic circuit with protection against eavesdropping by power analysis is provided. The electronic circuit includes: a storage element for storing a set of bits; a logic unit for processing the stored set of bits and providing a next state set of bits after two or more cycles, wherein in a first cycle, some of the stored set of bits are provided to the logic unit correctly and some are replaced by random values and in a last cycle, all of the stored set of bits are provided to the logic unit correctly; and a random bit generator that generates a random bit for each bit of the stored set of bits to determine which bits of the stored set of bits are to be provided correctly and which bits are to be replaced in each cycle.Type: GrantFiled: October 4, 2016Date of Patent: August 6, 2019Assignee: Winbond Electronics Corp.Inventors: Valery Teper, Nir Tasher
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Publication number: 20190207917Abstract: A memory subsystem includes a memory interface for accessing a non-volatile memory (NVM), a host interface for communicating with a host, and a processor. The processor is configured to calculate a signature over program code that is used by the host and is stored in the NVM, to verify, upon detecting a boot process performed by the host, whether the boot process is legitimate, and, only if the boot process was verified to be legitimate, to provide the signature to the host for authentication to a remote server.Type: ApplicationFiled: January 2, 2018Publication date: July 4, 2019Inventor: Nir Tasher
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Patent number: 10037441Abstract: An apparatus includes a processor and a bus encryption unit. The processor is configured to communicate information over a secured data bus, and to communicate respective addresses over an address bus. The bus encryption unit is configured to generate an encryption key based on multiple addresses that appeared on the address bus, and to encrypt the information communicated between the processor and the secured data bus with the encryption key.Type: GrantFiled: May 4, 2015Date of Patent: July 31, 2018Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Uri Kaluzhny, Nir Tasher
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Publication number: 20180081827Abstract: A memory system includes an interface, a non-volatile memory and a controller. The interface is configured to communicate over an unsecured communication link with an external host. The non-volatile memory is pre-programmed with a device identifier and a corresponding initialization key that are additionally stored in a database that resides externally to the memory system, and is securely accessible by the host. The controller is configured to send the device identifier to the host, to receive from the host, via the interface, binding information that was generated in the host, to generate, using at least the received binding information and the pre-programmed initialization key, a first binding key that matches a second binding key that is generated in the host based on an initialization key securely obtained by the host from the database, and to securely communicate with the host over the communication link using the first binding key.Type: ApplicationFiled: August 31, 2017Publication date: March 22, 2018Inventors: Itay Admon, Nir Tasher
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Publication number: 20180060607Abstract: A secured storage system includes a non-volatile memory and a controller. The non-volatile memory is configured to store a first data item and a respective first version identifier assigned to the first data item. The controller is configured to receive a second data item accompanied by a second version identifier and a signature, for replacing the first data item in the non-volatile memory, to authenticate at least the second version identifier using the signature, to make a comparison between the stored first version identifier and the second version identifier, and to replace the first data item with the second data item only in response to verifying that (i) the second version identifier is authenticated successfully, and (ii) the second data item is more recent than the first data item, as indicated by the comparison between the stored first version identifier and the authenticated second version identifier.Type: ApplicationFiled: August 7, 2017Publication date: March 1, 2018Inventors: Nir Tasher, Itay Admon
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Patent number: 9819657Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.Type: GrantFiled: June 14, 2016Date of Patent: November 14, 2017Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman, Uri Kaluzhny
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Publication number: 20170214520Abstract: An electronic circuit with protection against eavesdropping by power analysis is provided. The electronic circuit includes: a storage element for storing a set of bits; a logic unit for processing the stored set of bits and providing a next state set of bits after two or more cycles, wherein in a first cycle, some of the stored set of bits are provided to the logic unit correctly and some are replaced by random values and in a last cycle, all of the stored set of bits are provided to the logic unit correctly; and a random bit generator that generates a random bit for each bit of the stored set of bits to determine which bits of the stored set of bits are to be provided correctly and which bits are to be replaced in each cycle.Type: ApplicationFiled: October 4, 2016Publication date: July 27, 2017Applicant: Winbond Electronics Corp.Inventors: Valery Teper, Nir Tasher
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Patent number: 9641491Abstract: A method includes generating a first sequence of data words for sending over an interface. A second sequence of signatures is computed and interleaved into the first sequence, so as to produce an interleaved sequence in which each given signature cumulatively signs the data words that are signed by a previous signature in the interleaved sequence and the data words located between the previous signature and the given signature. The interleaved sequence is transmitted over the interface.Type: GrantFiled: June 23, 2014Date of Patent: May 2, 2017Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Uri Kaluzhny, Nir Tasher
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Patent number: 9626529Abstract: A secure data storage device for preventing tampering with data stored thereon includes a two-dimensional memory array for storing data, the array includes a predetermined number of data words. Each data word includes a set of bits, and is associated with a single physical address in the memory array. A key storage area for storing a key of the data storage device is included in the device. The secure data storage device includes an address conversion unit configured to convert a logical address to a corresponding physical address which points to a location in the memory array. The device includes a bit mixing unit for mixing bit values of an input data word to obtain a mixed word value, such that the mixed word value is a rearrangement of the bit values of the input data word. The device is electrically connectable to a host.Type: GrantFiled: November 10, 2015Date of Patent: April 18, 2017Assignee: Winbond Electronics Corp.Inventors: Nir Tasher, Mark Luko, Uri Kaluzhny
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Patent number: 9523722Abstract: A monolithic integrated circuit device may include a supply voltage glitch detector for detecting improper supply voltage conditions. Advantageously, the detection threshold of the supply voltage glitch detector is adaptively set based on the mode of operation of the device or a particular part of the device, which is internally known to the device based on certain inputs received by the device, such as commands, interrupts, control signals, and so forth.Type: GrantFiled: June 2, 2014Date of Patent: December 20, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Valery Teper, Dennis Chin Cheng, Koying Huang
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Patent number: 9471413Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.Type: GrantFiled: January 24, 2016Date of Patent: October 18, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Uri Kaluzhny, Tsachi Weiser, Valery Teper
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Publication number: 20160294792Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Inventors: Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman, Uri Kaluzhny
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Patent number: 9455962Abstract: An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.Type: GrantFiled: June 11, 2014Date of Patent: September 27, 2016Assignee: WINBOND ELECTRONICS CORPORATIONInventors: Nir Tasher, Moshe Alon, Valery Teper, Ziv Hershman, Uri Kaluzhny