Abstract: A receiver includes an interface, a delay line and circuitry. The interface receives data symbols and a clock signal for strobing the data symbols at selected positions. The delay line produces from the clock signal a middle sampling signal, and early and late sampling signals that respectively precedes and succeeds the middle sampling signal. The circuitry samples the data symbols using the middle, early and late sampling signals to produce early and late error signals. Based on the early and late error signals the delay line delays the middle, early and late sampling signals by separate delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols, and to output the data symbols strobed using the middle sampling signal.

Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.

Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.

Abstract: An apparatus for data storage, includes circuitry and a plurality of memory cells. The circuitry is configured to store data in a group of multiple memory cells by writing multiple respective input storage values to the memory cells in the group, to read respective output storage values from the memory cells in the group after storing the data, to generate for the output storage values multiple respective confidence levels, to produce composite data that includes the output storage values, to test a predefined condition that depends on the confidence levels, upon detecting that the condition is met, to compress the confidence levels to produce compressed soft data, and include the compressed soft data in the composite data, and to transfer the composite data over an interface to a memory controller.

Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.

Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells organized in multiple Word Lines (WLs). The processor is configured to read a Code Word (CW) of an Error Correction Code (ECC) from a group of multiple memory cells belonging to a target WL, to calculate for a given memory cell (i) a first soft metric, depending on a first threshold voltage of a first neighbor memory cell in a first WL neighboring the target WL, and (ii) a second soft metric, depending on a second threshold voltage of a second neighbor memory cell in a second WL neighboring the target WL, to calculate a combined soft metric based on both the first and second soft metrics and assign the combined soft metric to the given memory cell, and to decode the CW based on the combined soft metric, to produce a decoded CW.

Abstract: A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

Abstract: An apparatus for data storage, includes circuitry and a plurality of memory cells. The circuitry is configured to store data in a group of multiple memory cells by writing multiple respective input storage values to the memory cells in the group, to read respective output storage values from the memory cells in the group after storing the data, to generate for the output storage values multiple respective confidence levels, to produce composite data that includes the output storage values, to test a predefined condition that depends on the confidence levels, upon detecting that the condition is met, to compress the confidence levels to produce compressed soft data, and include the compressed soft data in the composite data, and to transfer the composite data over an interface to a memory controller.

Abstract: An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.

Abstract: An apparatus includes a memory and one or more processors. The memory includes multiple memory blocks. The one or more processors are configured to read at least part of data stored in a group of one or more memory blocks, the data including multiple code words of an Error Correction Code (ECC) that is decodable using one or more processing elements selected from among multiple predefined processing elements. The one or more processor are further configured to decode one or more of the code words, and identify one or more of the predefined processing elements that actually participated in decoding the respective code words, and, based on cost-values associated with the identified processing elements, the cost-values are indicative of processing latencies respectively incurred by the identified processing elements, to make a decision of whether or not to refresh the one or more memory blocks in the group.

Abstract: A memory controller includes an interface and a processor. The interface communicates with memory cells that store data in predefined Programming Voltages (PVs). The processor is configured to produce observation samples that each includes (i) a target sample read from a target memory cell in a target Word Line (WL), and (ii) neighbor samples read from neighbor memory cells. Based on the observation samples, the processor is further configured to jointly estimate Cross-Coupling Coefficients (CCFs), by searching for CCFs that aim to minimize a predefined function of distances calculated between transformed observation samples that have been transformed using the CCFs and combinations of PVs that are closest to the respective transformed observation samples, to apply, based on the CCFs, cross-coupling cancelation to readout samples retrieved from the memory cells to produce enhanced readout samples, and to perform a storage operation related to reading data, using the enhanced readout samples.

Abstract: An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.

Abstract: A circuit arrangement including one or more processors configured to: detect a presence of one or more human object proximities based on sensor data; identify one or more coverage sectors of one or more antenna arrays, operably coupled to the one or more processors, in response to the detected presence of the one or more human object proximities; determine whether radio waves within the one or more identified coverage sectors satisfy a transmit power criteria; select one or more candidate coverage sectors of the one or more antenna arrays based the one or more identified coverage sectors; and determine at least one radio link quality for the radio waves of the one or more candidate coverage sectors.

Abstract: A circuit arrangement including one or more processors configured to: detect a presence of one or more human object proximities based on sensor data; identify one or more coverage sectors of one or more antenna arrays, operably coupled to the one or more processors, in response to the detected presence of the one or more human object proximities; determine whether radio waves within the one or more identified coverage sectors satisfy a transmit power criteria; select one or more candidate coverage sectors of the one or more antenna arrays based the one or more identified coverage sectors; and determine at least one radio link quality for the radio waves of the one or more candidate coverage sectors.

Abstract: A communication device includes an evaluator configured to evaluate one or more criteria, wherein a first criterion of the one or more criteria includes detecting an object, a determiner configured to determine one or more beam pairs from a plurality of potential beam pairs to use in communications with a second device based on the evaluation of the one or more criteria and transmit an indication of one or more partner-side beams of a selected beam pair of the one or more beam pairs to the second device, and a beam controller configured to adjust an antenna to communicate with the second device via a device-side beam of the selected beam pair.

Abstract: Methods, systems, and devices for narrowband random access in a wireless communications system are described. A narrowband receiver may be implemented in a base station and may be used to perform low signal to noise ratio (SNR) processing and carrier frequency offset (CFO) cancellation in order to detect or decode an access message transmitted by another wireless device, such as a user equipment (UE). SNR processing and CFO cancellation may involve mapping differential operations to one or more accumulators and computing intra-symbol group averaging for symbols groups. By processing the access message according to the described techniques, the base station may estimate a round trip delay (RTD) time between the base station and the UE.

Abstract: Methods, systems, and devices for wireless communication are described. A narrowband receiver may be implemented in a base station and may be used to perform low signal to noise ratio (SNR) processing and carrier frequency offset (CFO) cancellation in order to detect or decode uplink control information (UCI) transmitted by another wireless device, such as a user equipment (UE). As described herein, processing of the UCI may include SNR boosting, noise estimation, parallel processing of data and pilot symbols, and peak searches performed across sliding windows applied to multiple decoding hypotheses. By processing the UCI according to the described techniques, the base station may improve performance of a given wireless communications system.

Abstract: A Line Interface Unit (LIU) can communicate a number of electromagnetic waveforms consistently fitting into a variety of specific waveform masks, such as masks defined by ITU-T G.703. The LIU includes a transmit part that includes a feedback controller that facilitates the LIU outputting electromagnetic waveforms consistently fitting into the specific waveform masks. The feedback controller can compensate for changes in environmental conditions, such as supply voltage, line profile, line impedance per protocol, doping gradient, and temperature. Also, this feedback controller allows for avoiding constant hardware modifications to the LIU for adjusting to different protocols or masks. It also can enable the LIU to instantiate a great number of times, such as twenty-one times on the same die, where the transmit part performs the feedback controller independently for each instantiation.