Abstract: A substrate support configured to support a substrate having a diameter D comprises a first inner electrode and a second inner electrode that are each D-shaped, define a first outer diameter that is less than D, and are configured to be connected to an electrostatic chuck voltage to clamp the substrate to the substrate support. An outer electrode comprises a ring-shaped outer portion that surrounds the first inner electrode and the second inner electrode and a center portion that pass between the first inner electrode and the second inner electrode to connect to opposite sides of an inner diameter of the ring-shaped outer portion. The inner diameter of the ring-shaped outer portion is greater than the diameter D such that the inner diameter of the ring-shaped outer portion and intersections between the center portion and the ring-shaped outer portion are located radially outside of the diameter D of the substrate.

Abstract: An apparatus to determine occurrence of an anomalous plasma event occurring at or near a process station of a multi-station integrated circuit fabrication chamber is disclosed. In particular embodiments, optical emissions generated responsive to the anomalous plasma event may be detected by at least one photosensor of a plurality of photosensors. A processor may cooperate with the plurality of photosensors to determine that the anomalous plasma event has occurred at or near by a particular process station of the multi-station integrated circuit fabrication chamber.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: A method for cleaning a semiconductor structure includes subjecting a semiconductor structure to an aqueous solution including at least one fluorine compound, and at least one strong acid, the aqueous solution having a pH of less than 1. In one embodiment, the aqueous solution includes water, hydrochloric acid, and hydrofluoric acid at a volumetric ratio of water to hydrochloric acid to hydrofluoric acid of 1000:32.5:1. The aqueous solution may be used to form a contact plug that has better contact resistance and improved critical dimension bias than conventional cleaning solutions.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally, with an inorganic acid, and a pH of 1 or less.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: A method for cleaning a semiconductor structure includes subjecting a semiconductor structure to an aqueous solution including at least one fluorine compound, and at least one strong acid, the aqueous solution having a pH of less than 1. In one embodiment, the aqueous solution includes water, hydrochloric acid, and hydrofluoric acid at a volumetric ratio of water to hydrochloric acid to hydrofluoric acid of 1000:32.5:1. The aqueous solution may be used to form a contact plug that has better contact resistance and improved critical dimension bias than conventional cleaning solutions.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (GaN) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (InGaN) material directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN, and P-type GaN materials has a non-planar surface.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.

Abstract: A method of etching polysilicon includes exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal nitride, Pt, and Au under conditions effective to etch polysilicon from the substrate. In one embodiment, a substrate first region comprising polysilicon and a substrate second region comprising at least one of a conductive metal nitride, Pt, and Au is exposed to a solution comprising water and HF. The solution is devoid of any detectable conductive metal nitride, Pt, and Au prior to the exposing. At least some of the at least one are etched into the solution upon the exposing. Then, polysilicon is etched from the first region at a faster rate than any etch rate of the first region polysilicon prior to the etching of the at least some of the conductive metal nitride, Pt, and Au.

Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.