Patents by Inventor Niraj Shantilal PALIWAL

Niraj Shantilal PALIWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Allocation of data sub-tensors onto hardware sub-arrays
    Patent number: 12093155
    Abstract: Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: September 17, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Hee Jun Park, Bohuslav Rychlik, Niraj Shantilal Paliwal
  • ALLOCATION OF DATA SUB-TENSORS ONTO HARDWARE SUB-ARRAYS
    Publication number: 20230100036
    Abstract: Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Hee Jun PARK, Bohuslav RYCHLIK, Niraj Shantilal PALIWAL