Patents by Inventor Niranjan Anant Pol
Niranjan Anant Pol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880568Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.Type: GrantFiled: December 28, 2021Date of Patent: January 23, 2024Assignee: SEAGATE TECHNOLOGY LLCInventors: Rajesh Maruti Bhagwat, Nahoosh Hemchandra Mandlik, Niranjan Anant Pol, Hemantkumar Vitthalrao Mane
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Publication number: 20230418685Abstract: Method and apparatus for offloading upstream processing tasks to peer groups of downstream data storage devices. A peer control circuit forms a peer group of storage devices in response to a detected processing bottleneck associated with a network controller. One of the storage devices in the peer group is designated as a primary device, and is responsible for interface communications, for subdividing the processing task for execution by secondary devices in the peer group, and coordinating overall execution. The peer group and the processing task are selected to avoid or minimize the processing bottleneck at the network controller level while maintaining ongoing data transfer performance at the storage device level. A list of available device resources and capabilities may be maintained by the peer control circuit. Offloaded tasks can include data rebuilds, cryptographic functions, new device authentication operations, and the like. Multiple overlapping peer groups can be formed as needed.Type: ApplicationFiled: June 23, 2023Publication date: December 28, 2023Inventors: Jason Wayne Kinsey, Hemant Vitthalrao Mane, Niranjan Anant Pol, Marc Timothy Jones, Jason Matthew Feist
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Publication number: 20230259661Abstract: A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.Type: ApplicationFiled: April 4, 2022Publication date: August 17, 2023Inventors: Rajesh Maruti Bhagwat, Hemant Vitthalrao Mane, Avinash Suresh Pisal, Niranjan Anant Pol
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Publication number: 20230152970Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.Type: ApplicationFiled: December 28, 2021Publication date: May 18, 2023Inventors: Rajesh Maruti BHAGWAT, Nahoosh Hemchandra MANDLIK, Niranjan Anant POL, Hemantkumar Vitthalrao Mane
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Patent number: 11630779Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: GrantFiled: November 17, 2021Date of Patent: April 18, 2023Assignee: Seagate Technology, LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Publication number: 20230112448Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide one or more data management functionality. The CSD interfaces with a plurality of storage controllers for parallel data management functionality applied to a corresponding plurality of memory devices. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.Type: ApplicationFiled: December 28, 2021Publication date: April 13, 2023Inventors: Hemantkumar Vitthalrao MANE, Niranjan Anant POL, Nahoosh Hemchandra MANDLIK, Avinash Suresh PISAL
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Publication number: 20220244851Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.Type: ApplicationFiled: February 2, 2021Publication date: August 4, 2022Inventors: Hemant MANE, Rajesh Maruti BHAGWAT, Avinash Suresh PISAL, Niranjan Anant POL
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Publication number: 20220075729Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Patent number: 11221956Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: GrantFiled: May 31, 2017Date of Patent: January 11, 2022Assignee: Seagate Technology LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Publication number: 20180349040Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: Seagate Technology LLCInventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
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Patent number: 8726108Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.Type: GrantFiled: January 12, 2012Date of Patent: May 13, 2014Assignee: LSI CorporationInventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy, Niranjan Anant Pol, Vineet Sreekumar
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Publication number: 20130185607Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: lSI CorporationInventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy, Niranjan Anant Pol, Vineet Sreekumar