Patents by Inventor Niranjan Behera
Niranjan Behera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11670361Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.Type: GrantFiled: July 15, 2021Date of Patent: June 6, 2023Assignee: Synopsys, Inc.Inventors: Moon-Hae Son, Niranjan Behera
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Patent number: 11481255Abstract: Provided is a method, computer program product, and coherent computer system for improving memory management by establishing cooperation between an operating system and a coherent accelerator device (CAD). The CAD may retrieve a set of work elements for completion from a work queue. The CAD may determine a length of time required to complete the set of work elements. The CAD may identify a set of memory pages needed for completing the set of work elements. The CAD may communicate the set of memory pages and the length of time required to complete the set of work elements to a virtual memory manager.Type: GrantFiled: September 10, 2019Date of Patent: October 25, 2022Assignee: International Business Machines CorporationInventors: Chetan L. Gaonkar, Niranjan Behera, Geeta Devi Akoijam, Vamshikrishna Thatikonda
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Publication number: 20220020420Abstract: An integrated circuit includes a memory cell array coupled to a bitline and a first wordline and a negative-type metal-oxide-semiconductors (NMOS) pull-down structure coupled to the bitline and PMOS transistors. The positive-type metal-oxide-semiconductors (PMOS) transistors may be coupled to a second wordline, where a logic value carried on the second wordline is based on a logic value carried on the first wordline, and the PMOS transistors are structured to pre-charge respective drains of the NMOS pull-down structure to a high logic value based on a low logic value carried on the second wordline. The NMOS pull-down structure may be structured to discharge the bitline based on a high logic value carried on the second wordline.Type: ApplicationFiled: July 15, 2021Publication date: January 20, 2022Inventors: Moon-Hae Son, Niranjan Behera
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Publication number: 20210073033Abstract: Provided is a method, computer program product, and coherent computer system for improving memory management by establishing cooperation between an operating system and a coherent accelerator device (CAD). The CAD may retrieve a set of work elements for completion from a work queue. The CAD may determine a length of time required to complete the set of work elements. The CAD may identify a set of memory pages needed for completing the set of work elements. The CAD may communicate the set of memory pages and the length of time required to complete the set of work elements to a virtual memory manager.Type: ApplicationFiled: September 10, 2019Publication date: March 11, 2021Inventors: Chetan L. Gaonkar, Niranjan Behera, Geeta Devi Akoijam, Vamshikrishna Thatikonda
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Patent number: 9966131Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.Type: GrantFiled: August 21, 2015Date of Patent: May 8, 2018Assignee: Synopsys, Inc.Inventors: Dharmesh Kumar Sonkar, Niranjan Behera
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Publication number: 20170053695Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.Type: ApplicationFiled: August 21, 2015Publication date: February 23, 2017Inventors: Dharmesh Kumar Sonkar, Niranjan Behera
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Systems and methods for reducing memory array leakage in high capacity memories by selective biasing
Patent number: 7940550Abstract: A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.Type: GrantFiled: September 14, 2009Date of Patent: May 10, 2011Assignee: Synopsys, Inc.Inventors: Niranjan Behera, Deepak Sabharwal, Yong Zhang -
SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING
Publication number: 20110063893Abstract: A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.Type: ApplicationFiled: September 14, 2009Publication date: March 17, 2011Inventors: Niranjan Behera, Deepak Sabharwal, Yong Zhang -
Patent number: 7904766Abstract: Improving statistical yield of a system-on-a-chip. The system-on-a-chip includes several memory systems. Each memory system includes a large number of memories. The memories are tested to identify any faulty memories. One or more margins of the faulty memories are then varied and the memories are then tested again.Type: GrantFiled: December 6, 2007Date of Patent: March 8, 2011Assignee: Synopsys, Inc.Inventors: Niranjan Behera, Alexander Shubat
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Patent number: 7788551Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.Type: GrantFiled: August 8, 2008Date of Patent: August 31, 2010Assignee: Virage Logic Corp.Inventors: Niranjan Behera, Bruce L. Prickett, Jr., Yervant Zorian
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Patent number: 7539590Abstract: A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.Type: GrantFiled: April 13, 2006Date of Patent: May 26, 2009Assignee: Virage Logic Corp.Inventors: Niranjan Behera, Bruce L. Prickett, Jr.
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Publication number: 20080301507Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.Type: ApplicationFiled: August 8, 2008Publication date: December 4, 2008Applicant: Virage Logic Corp.Inventors: Niranjan Behera, Bruce L. Prickett, JR., Yervant Zorian
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Patent number: 7415641Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.Type: GrantFiled: November 5, 2003Date of Patent: August 19, 2008Assignee: Virage Logic Corp.Inventors: Niranjan Behera, Bruce L. Prickett, Jr., Yervant Zorian
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Patent number: 7139204Abstract: A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells. Accordingly, each multi-port memory cell is connected to one word-line and two bit-lines per read/write port. The memory device includes memory testing logic to perform a first memory access operation (e.g., read/write) at a first port of the multi-port memory cell while the memory cell is in a stressed condition. For example, the first memory access operation occurs while a second memory access operation is emulated on a second port. Moreover, the memory access operations occur at a frequency that is substantially equivalent to a maximum operating frequency of the dual-port memory device.Type: GrantFiled: June 6, 2005Date of Patent: November 21, 2006Assignee: Virage Logic CorporationInventor: Niranjan Behera
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Publication number: 20060190208Abstract: A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.Type: ApplicationFiled: April 13, 2006Publication date: August 24, 2006Inventors: Niranjan Behera, Bruce Prickett
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Patent number: 7031866Abstract: A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.Type: GrantFiled: November 5, 2003Date of Patent: April 18, 2006Assignee: Virage Logic Corp.Inventors: Niranjan Behera, Bruce L. Prickett, Jr.
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Patent number: 6646933Abstract: A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input circuit is coupled to the one or more defective memory columns.Type: GrantFiled: July 31, 2002Date of Patent: November 11, 2003Assignee: Virage Logic CorporationInventors: Alexander Shubat, Niranjan Behera, Izak Kense
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Patent number: 6519202Abstract: A method, system, and apparatus exist which couple a first group of non-redundant memory columns to a non-redundant input-output circuit and couple a second group of redundant memory columns to a redundant input-output circuit. A fewer amount of memory columns exist in the second group of redundant memory columns than in the first group of non-redundant memory columns. A first fuse indicates whether one or more memory columns are defective in a group of non-redundant memory columns coupled to the non-redundant input output circuit. Also, a second fuse couples to a first circuit. The first circuit identifies which sub-input-output circuit is coupled to the one or more defective memory columns.Type: GrantFiled: June 29, 2001Date of Patent: February 11, 2003Assignee: Virage Logic CorporationInventors: Alexander Shubat, Niranjan Behera, Izak Kense
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Patent number: 6396760Abstract: An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.Type: GrantFiled: March 16, 2001Date of Patent: May 28, 2002Assignee: Virage Logic CorporationInventors: Niranjan Behera, Shreekanth K. Sampigethaya