Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

Abstract: A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal.

Abstract: A wireless communication device can include an antenna configured to sense a radio frequency (RF) signal. The wireless communication device can include signal estimation circuitry configured to generate estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include multi-tone generator circuitry coupled to the signal estimation circuitry and configured to generate a composite spur cancellation signal based on the estimates of amplitude and frequency for unmodulated spurs within the RF signal. The wireless communication device can further include adder circuitry configured to subtract the spur cancellation signal from the RF signal to generate a spur cancelled signal.

Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

Abstract: Described herein are architectures, platforms and methods for enhancing range and increasing data rates during near field communication (NFC) related functions or transactions.

Abstract: Described herein are architectures, platforms and methods for implementing low-power detection of a near field communication (NFC) card or tags. In particular, an NFC antenna is integrated with at least one transistor to form an oscillator. A substantial decrease in oscillator's oscillation indicates presence or detection of the NFC card or tag.

Abstract: Described herein are architectures, platforms and methods for enhancing human body communications (HBC) mode during near field communication (NFC) related functions or transactions. Optimization of the HBC communications system can include a radio frequency (RF) tuning circuitry to generate a voltage-based resonant frequency at respective capacitive pads of transmitting and receiving devices. The RF tuning circuitry includes a series connected capacitor-inductor driver that may be constructed within or outside of an NFC module circuitry or NFC silicon.

Abstract: Described herein are architectures, platforms and methods for implementing low-power detection of a near field communication (NFC) card or tags. In particular, an NFC antenna is integrated with at least one transistor to form an oscillator. A substantial decrease in oscillator's oscillation indicates presence or detection of the NFC card or tag.

Abstract: Described herein are architectures, platforms and methods for enhancing human body communications (HBC) mode during near field communication (NFC) related functions or transactions. Optimization of the HBC communications system can include a radio frequency (RF) tuning circuitry to generate a voltage-based resonant frequency at respective capacitive pads of transmitting and receiving devices. The RF tuning circuitry includes a series connected capacitor-inductor driver that may be constructed within or outside of an NFC module circuitry or NFC silicon.

Abstract: Described herein are architectures, platforms and methods for calibrating a near field communication (NFC) reader/writer device using a modulation feedback apparatus for tuned antenna configurations.

Abstract: Described herein are architectures, platforms and methods for calibrating a near field communication (NFC) reader/writer device using a modulation feedback apparatus for tuned antenna configurations.

Abstract: Described herein are architectures, platforms and methods for detecting near field communication (NFC) cards/tags by a NFC enabled device, using a coupled impedance signature unique to the NFC cards/tags and the NFC enabled device.

Abstract: Described herein are architectures, platforms and methods for detecting near field communication (NFC) cards/tags by a NFC enabled device, using a coupled impedance signature unique to the NFC cards/tags and the NFC enabled device.

Abstract: Described herein are architectures, platforms and methods for enhancing range and increasing data rates during near field communication (NFC) related functions or transactions.